DFF Hold Violation Problem

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Boyenju

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I have two types of circuits
Type 1

Type2

I was told that i have hold violation in the 2nd DFF(right one) in both of them, where would you put buffers in order to solve the hold violation?
i would be very happy if some explain me this with an clk diagram or smthing.
thank you.
 

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When clock signal turns high (at +ve clock edge) to activate a DFF, the DFF will consume the input & produce the output.
Hold violation on 2nd DFF means that when the clock signal goes high (+ve clk edge), new output signal from 1st DFF reached 2nd DFF's input too fast, so fast that 2nd DFF not yet able to consume the old input.

You can put buffer between 1st & 2nd DFF to solve this problem.
 

i thought of putting a buffer between the two DFF or to put a buffer b4 the clk enter to DFF1 that's for type 2 ,
and for type 1 i thought of putting the same as i mentioned for type2 and another one on the Feedback b4 the enter to the 1st DFF.
what do you think ?
 

I would suggest:
type 1: put buffer between DFF1 to DFF2.
type 2: put buffer between DFF1 to DFF2; and also put buffer between DFF2 to DFF1 if you see hold issue here.

The method of putting buffer before clk of DFF1 (playing with clock skew) will work for the design in your diagram, but it will affect the timing path going into input of DFF1 (which is not showed in your diagram).
 

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