devices mismatch in LVS check

[Alex_Zhan]

Hello everyone, when I do LVS check in cadence, I find this problem in the picture. This layout can pass the DRC check, and I am sure the devices in the layout are the same as the ones in schematic.
Does anyone know the reason? Thank you deeply!

 

[dick_freebird]

Like it says right up top, bad wiring.

Start probing layout nets attached to the device and
look for shorts, opens first. The problem may be at the
other end of the wire, not at the device named.

 

[Alex_Zhan]

Like it says right up top, bad wiring.

Start probing layout nets attached to the device and
look for shorts, opens first. The problem may be at the
other end of the wire, not at the device named.

Thank you sincerely, it does help me.
I solved this problem by checking the labels of the ports which connect these transistors in the layout.

 

[viewcart]

The LVS tool should give you a report of the mismatch. These reports are often very difficult to decipher, but in the context of a two transistor circuit, you should be able to figure out what it thinks the difference is. Alternatively, look directly at the netlists being generated from the layout and the schematic, which should either be available from the results viewer GUI, or by opening the run directory in the terminal and looking for some files ending with .cdl or .sp.