Deterministic Results with Design Compiler

[ebrahimi.khoy]

I run synopsys design compiler for a relatively large processor core and every time I get a different netlist. Is there any why to get deterministic results from this tool?

 

[rca]

Normaly if you have the same constraints, the same rtl code, the same tool version and the same script, you should have the save netlist.

 

[ebrahimi.khoy]

This is not true for Design compiler. I guess they implemented an stopping condition based on the time. Since the timing is dependent on the other running tasks, it become non-deterministic.

 

[sharath666]

The results need not be deterministic. The tool uses a random seed every time.

 

[ebrahimi.khoy]

Is there any way to adjust this seed?

The results need not be deterministic. The tool uses a random seed every time.

 

[sharath666]

No way at least as far as I know.

 

[jt_eaton]

The amazing thing is how few designers really understand this behaviour. I heard a talk in a eda conference where the researcher did multiple compiles
of the same logic and saw results vary by up to 10%.

John Eaton

 

[ebrahimi.khoy]

The amazing thing is how few designers really understand this behaviour. I heard a talk in a eda conference where the researcher did multiple compiles
of the same logic and saw results vary by up to 10%.

John Eaton

Do you remember the paper title for that presentation?

 

[jt_eaton]

Do you remember the paper title for that presentation?

It was an after dinner speech, there was no paper.