Can you elaborate on your design requirements? Are you implementing this design using a FPGA or CPLD?
Really no need for additional gates, unless you need a latch or a buffer to retain the signal state, of course technically at that point it no longer is classified as a combinational logic, but as sequential logic.
Well, you really don't need a circuit element to do that in FPGAs. Just a wire connecting the LSB of the 8-bits number to the ODD Signal. But better help could be provided if you could throw some more light upon your requirements.