[SOLVED] Details of Crosstalk delay and Crosstalk noise

Hi Friends,
I would like to know what is crosstalk delay and crosstalk noise?
what are the causes of these?
what are the remedies?
How is crosstalk delay analysis and noise analysis done?
What are the inputs and outputs?
Please elaborate on differences between crosstalk delay and crosstalk noise.

Thanks,
Sowmya

Hi,
# In our circuit design the coupling capacitance may be form, when the distance between two nets/metals/wires are too norrow, Because of the electric field difference between the two nets/wires. These coupling capacitances caused the crosstalk.
# It will make the crosstalk delay and crosstalk noise due to the wire load increasing.
# By making the proper spacing between the wires/nets, we can reduce the crosstalk. That's what we are doing in the Design Rule Check. (I think)

rgds,
Nantha.

Hi Sowmya & Nantha,

If two signal or clock nets are closer enough to each other, the effect of coupling capacitance between them leads to crosstalk.

Crosstalk delay: Let's say one net is switching at faster rate (time taken for signal level to rise from 0 to 1 is less) and other net switching at slower rate (time taken for signal level to rise from 0 to 1 is less), due to coupling cap...faster switching net effects in speedingup of slower net.

Let say one net is switching at faster rate from 0 to 1 and other adjacent ramps down from 1 to 0 at slower rate. The effect of first net will delay ramping down of slower net further.

Think of these kind of situations on the chip for crosstalk delays....I will not elaborate further on this...just imagine...

Crosstalk noise: When one net is idle and its adjacent net is switching form 0 to 1, there is possiblilty of unwanted signal transition for finite time induced in idle net due to coupling cap. If this unwanted transition is within noisemargin of your technology then it will corrupt the logics.

Remedies to encounter these two effects:

1. Move interacting nets apart in layout. (if your layout is not congested)
2. Shield the nets using proper sheilding metal (Let me know what metal is usually used for shieiding purpose).
3. Re-route tge interacting nets.

You can add to this list....if you have any more remedies....

Crosstalk delay analysis: PT-SI tool does this based on timing constraints. It needs SPEF and incremental SDF to do this. I can elaborate on this...let me know if you want to...

Crosstalk noise analysis: I believe libs should have noise models to do this. Don't have much idea on this. Please let me know if you know something on this.

Inputs: PT-SI license, SPEF and inc SDF, Proper timing constraints, noise models.
Outputs: Violating timing paths.

Regards,
Eshwar.

Hi eshwartt,

Thanks for your response.

SPEF- Standard Parasitic Exchange Format is an IEEE standard for representing parasitic data of wires in a chip in ASCII format. Resistance, capacitance and inductance of wires in a chip are known as parasitic data. i don't know further details...!

If u dont mind can u elaborte in details about this..? And at which time they will do this Crosstalk analysis? After RC extraction or at the timing of Routing or when?

Thanks in advance,
Nantha

Please see my comments in-line.......

Hi eshwartt,

Thanks for your response.

SPEF- Standard Parasitic Exchange Format is an IEEE standard for representing parasitic data of wires in a chip in ASCII format. Resistance, capacitance and inductance of wires in a chip are known as parasitic data. i don't know further details...!
[Eshwar]: SPEF and Incremental SDF are sufficient for crosstalk analysis. If layout tool can provide DSPEF it is very good. These are annotated into PT-SI or GT-SI tool along with constraints. PT-SI first estimates timing windows where nets will interact based on clock constraints set in design and reports the crosstalk effect on delay in timing reports.

If u dont mind can u elaborte in details about this..? And at which time they will do this Crosstalk analysis? After RC extraction or at the timing of Routing or when?
[Eshwar]: I never mind to share my knowledge. In any Chip, timing violations are fixed without doing crosstalk analysis first i.e using PrimeTime. When timing is nearing closure...They will enable SI checks to look at timing violations in PT. Clocks groups in constraints drive the SI tool to estimate timing windows where nets intearct to most extent. Let me know if you need more details on this..

Thanks in advance,
Nantha
[Eshwar]:
Regards,
Eshwar.

Hi

It's useful information for me.. Thanks Eshwar..

Hi Eshwar,
I am not sure if the shielding is done using a special metal. Usually the nets having a high probability of switching are shielded using nets with no switching properties like power lines Vcc and Vss.

Hi All,

there are few ways to reduce or remove crosstalk
like:-

1) double spacing
2) reduce parallalism
3) switch to other metal layer
4) insert buffer in victim net
5) upsize driver of victim
6) downsize driver of aggressor
7) shielding the victim net

Q-1) Now please list it out priority wise
means which option we should opt first and then go for next option likewise

Q-2) In option 1) and 7) both we are going to waste one routing track, now tell me which one I should opt first and why?

Regards
Jitendravlsi

Just a quick question regarding crosstalk and noise. do we need two dynamically simulate these to effects, and in which situation?