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OCV: On chip Variation of Voltage, temperature, Process.
When a chip is fabricated, it is present with other identical chips on the wafer. There are some variations which happen on the complete wafer, these are referred to as global variations, and the variations which happen on the chip only are said to be OCV. We need to take care of these variations in STA because these variations will effect the arrival and the required times if the signals in the timing paths. We apply OCV in STA with the help of Derates (scaling of the launch paths and capture paths depending on the check-setup or hold-).
AOCV: Advanced OCV=> This is also called location aware OCV In this we apply derating values on the cells/nets based on the logic depth from the common fanout point of the clock, ie: the point from which the launch and the capture clock bifurcate. This type of OCV needs AOCV tables in the timing libraries.
This OCV is more accurate and we can avoid adding unnecessary pessimism which gets added using OCV
From where does this derating values comes from ?? How much derate should i specify ?? On what factors does it depends upon ? How do we get this value ??
OCV value usually comes from CHIP vendor after doing multiple simulations, legacy design data and scaling factor. (TSMC, GF).
Generally derate values vary from 5 -10% depending upon your chip, design, application and technology.
f you are top level designer, you should know your Temp, voltage and other parameters at the same time process variation from foundry and with simulation you can get a graph for best case and worst case values for device (bell curve.)
You have to use it depending upon accuracy you need.
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