Detailed steps of Timing Optimization for STA Engineer

[ivlsi]

Hello All,

Could someone list the steps (one by one), which should be done by STA Engineer for timing optimization of the various logic paths?

Let's say something like following:
1) Check whether the path true or false
2) Check whether the path is over-constrained
3) ...

Timing optimization methods:
1) try to release constraints
2) try to use the cells with higher fan out
3) try to clone the logic
4) try to re-time/re-balance the logic
5) ...

Thank you!

 

[birdy123]

Re: [STA] Timing Optimization

Hi Dmitryl,

It will be good you you refer any of the STA userguide of any EDA tool. Just for understanding the flow you can also refer..

STA using EDA tool part1

STA using EDA tool part2

I hope it will help you. Let me know in case you have any specific question.

 

[dftrtl]

Re: [STA] Timing Optimization

First step to check is check_timing to see any valid path is unconstrained.
Next step would be picking a clock group one at a time and fixing the SETUP violations.
Once SETUP is clean we move to fix the HOLD violations.

 

[subhash_chevella]

Re: [STA] Timing Optimization


In any design, hold violations are critical than setup violations.
If design is clean w.r.t setup & violating hold, that design doesn't work. Functionally failure device.
Parallely, we need to fix the setup & hold violations across all corners.
Its better to close hold first & then move on to setup.
If hold is clean & setup is violating, we can use that device with lower frequency.

 

[dftrtl]

Re: [STA] Timing Optimization

Both setup and Hold are important for design closure.
Generally bench mark for your design will be what frequency it is working. So I feel setup has more weightage than hold.

 

[googler123]

Re: [STA] Timing Optimization

Thanks,,www.semicic.com

 

[ivlsi]

Re: [STA] Timing Optimization

"better to fix hold violations first & then move on to setup violations" - Why?

 

[dftrtl]

Re: [STA] Timing Optimization

Which ever way you do no issue, but adding buffers for fixing hold in divergent path is standard. If you have fixed setup critical paths and when you move to HOLD you will have a picture what you have seen fixing setup.

 

[subhash_chevella]

Re: [STA] Timing Optimization


First, we will try to fix @ desired frequency only.
As we are moving down, it will be difficult to close the design @ desired frequency.
At this critical stage, we will fix the all hold violations to make sure your design is functionally correct. Then we will move to setup fixes again.
If we are not able to clean setup in any manner, we will relax the frequency of operation (last option) depending upon the customer requirement.

If your design is clean w.r.t setup and hold violations are there, design will not be functionally correct. We can blindly throw the design into dustbin.
But if hold is clean, setup violations are there, we can relax the frequency of operation. Functionally correct but frequency of operation is less.

regards,
Subhash C