madmax
Newbie level 6
Hi ,
I'm working in the embedded application.I design using FPGA's.In one of my design, there are lots of interrupts given to microprocessor. Only one interrupt is connected to the Microprocessor interrupt pin physically.But microprocessor identifies the different interrupts by reading the master register(8 bits) and its corresponding slave registers inside the FPGA design.Interrupts are having priority also.
Is there any material which describes how to design for handling interrupts for these type of application.Issues when designing with interrupts
For example : when the interrupt pin should be asserted low after reading the
master register or the corresponding slave register
Thanks in Advance ,
Max
I'm working in the embedded application.I design using FPGA's.In one of my design, there are lots of interrupts given to microprocessor. Only one interrupt is connected to the Microprocessor interrupt pin physically.But microprocessor identifies the different interrupts by reading the master register(8 bits) and its corresponding slave registers inside the FPGA design.Interrupts are having priority also.
Is there any material which describes how to design for handling interrupts for these type of application.Issues when designing with interrupts
For example : when the interrupt pin should be asserted low after reading the
master register or the corresponding slave register
Thanks in Advance ,
Max