Designing an inverter with a particular delay for duty-cycled clock generation

[Arpit_Bal]

Is there any method by which we can design an inverter with a particular delay (roughly in 100s of picoseconds), as I want to generate a duty-cycled clock as an incoming signal in one of my analog blocks? (P.S. I want to use the minimum number of inverters to achieve that delay.)

 

[D.A.(Tony)Stewart]

What is the fastest gate you have now?

how about 280 ps ?

SN75LVCP600SDSKR CML 0.5V to 1.5V​

 

[KlausST]

Hi,

the terminology "inverter" has several meanings.

If you talk about logic inverters = digital, then why post in th "analog circuit design" section?
Then I´m not sure if you are talking about circuit or IC design?

In either case ... isn´t technology, supply voltage, input signal specification, indeed any specification .. essential for us to know?

Klaus

 

[FvM]

Are you designing integrated digital logic, then we would move the question to IC design. If the question is about designing the inverter from discrete transistors or using of-the-shelf digital ICs, there's no dedicated digital circuit design section at Edaboard.

Please clarify what "design an inverter" means for you.

 

[D.A.(Tony)Stewart]

I'm afraid your question is illogical with microwave duty cycles in an analog circuit without awareness of realistic parameters.

 

[D.A.(Tony)Stewart]

By the way, we know all logic devices are analog, we just don’t have any clue what input/output you expect and its purpose.