Designing a CMOS op-amp

I have an assignment to design a CMOS op-amp for uni. My problem is I don't know where to even begin with the design process.
The following has been given:

• DC Loop Gain: >80dB
• Phase Margin: >60*
• Gain BW product: >15MHz
• Power Dissipation Target: 1mW
• Supply Voltage: 3.3V
• Bias Current: 100uA
• Common-mode ref voltage: 1.5V
• Load: 10pF to gnd
• Cadence c35b4 model (35nm process)

What I understand so far:
I'm familiar with the transistor level operation of a CMOS op-amp. I know with a capacitive load that a two-stage op-amp is sufficient.
Av is the non-dB value of DC Loop Gain, i.e. 10,000 I think.
Phase margin is determined by Cc.

I don't really know where to start with the design process for sizing the transistors though, or what assumptions I need to make for other parameters not given in the spec.

Any pointers in the right direction would be really welcome!

Dear cork

I could tell you from where you have to start, but I got this from the book of CMOS analog circuit design for Allan Holberg. He gave a complete procedure with full explanation not only for the two stage, but for different Oamp topologies. Therefore, I highly recommend you to read this book. the design procedure is given in chapter 6.
Just as a note, the procedure from this book are followed by most of the analog circuit designer

I think you should start with designing dc loop gain in respect of bias current and supply voltage.

start by looking at your specs and determining which is on the more strict side. 10Pf to ground is very large. however no slewing or settling time is required, so i guess you can ignore slew rate limitations (big advantage since this would normally eat into your power number).
i also see no noise number requirements , also a big plus for you since that would also eat into your power.I agree with your assessment that a twostage op should be capable, folded cascode wont do the trick here... unless you do active cascoding..
you are way oversimplifying the phase margin, this is not a simple based on cc , but you can use cc and rc to influence it. (the load cap will be a large influence as well).
typically size is influenced by noise, gain, bw and slew rate. larger input pair ratios = larger gm (larger gain), larger slew requires more current when in turn requires a revisit to sizing to preserve operating points. noise is proportional to area. and bw impacted by the parasitic Caps which increase with device size (also heavily affects phase margin). as i said before noise and slew is not a concern, so your sizing should be based solely on gain and bw and pm. with your large loading the power will come from making it broadband enough to achieve 15Meg with a 10pF load.
just remember typically gain and bw is a tradeoff( more current typically increased BW and decreases Gain), so dont give yourself 1Ghz bw or your gain will be hurting, and vice versa with getting 90+dB gain or something.
also in case you are thinking the gain should increase with current, just remember in a diff pair/cs amp the gain is gm *ro, gm increased by sqrt(I), ro decreased by I. so your overall gain will decrease by sqrt(I). many seem to forget this and focus solely on gm.
also note that you only have .66mW for your amp because the stupid bias is consuming .33mW or 33% of your power. I recommend a sc fb to prevent any other loss of power.
Enjoy your project and take full advantage of no settling or slew or noise requirements
-Pb

Thanks guys. I'm attempting to follow the design procedure in the Allen and Holberg book.
When the design is left so open ended, how would I choose appropriate oxide capacitance, threshold voltage, oxide thickness etc etc? The approach in the book assumes I have these values to hand.

going a bit back to basics but you do not choose these. the process determines these. look up your c35b4 models(which btw are AMS models, cadence is just the tool you are designing in), you will see the values you need.
so yes you do have these values at hand.

-Pb

Dear cork

These values are defined by the technology models that you are implementing your design under it. It is always documented or in some case you have to extract it by yourself if it is not given.

cork-spotters said:

Thanks guys. I'm attempting to follow the design procedure in the Allen and Holberg book.
When the design is left so open ended, how would I choose appropriate oxide capacitance, threshold voltage, oxide thickness etc etc? The approach in the book assumes I have these values to hand.

Click to expand...

Thanks again. Making progress here after receiving pointers from you guys. School-boy errors!
What is beta referring to in the A&H book? It is used in voltage calculations here. Only beta I've come across in the IC design world has been for the gain of a BJT...

Beta is the feedback factor , i actually put a post on here a week or so ago with my own confusion on calculating Beta. Its used when doing loop gain sims, loop gain is A*B, A is openloop gain, beta is the feedback factor(if you remove the amp output from the output and place a 1v ac source on the output, beta is the ac value at the summing junction of the amp( think voltage divider).

Is it calculable before building the op-amp?

I guess I am a little confused, when you mentioned the 80dB I thought you were referring to open loop gain, but it appears you are referring to loop gain, AB. if that is the case then you should have been given some type of loop requirement( buffer, gain, attenuation, etc). But this makes the 80dB tougher because Beta is usually a fraction, meaning AB < A. If there is a loop gain requirement, I'm sure your class must have gone over what beta is before putting a requirement spec on AB as well as how to solve for it. most sim tools do not simulate AB, you have to sim A and then B and then multiply them yourself.

Would that be what I'd normally have said is Av = gm1*gm2? Where gm1 and gm2 are equal to A and B in your post?

The only other piece of information given is Vcm = 1.5V applied to the positive input.

No No No, what he is asking is about the beta of the technology parameter. beta is the transconductance parameter

prestonee said:

Beta is the feedback factor , i actually put a post on here a week or so ago with my own confusion on calculating Beta. Its used when doing loop gain sims, loop gain is A*B, A is openloop gain, beta is the feedback factor(if you remove the amp output from the output and place a 1v ac source on the output, beta is the ac value at the summing junction of the amp( think voltage divider).

Click to expand...

That beta is only in bjt though. unless he is designing a bjt 2 stage amplifier... or unless the book he is referencing is referencing bjt amp design..

- - - Updated - - -

I guess he needs to give of context on what he means specifically when he states "What is beta referring to in the A&H book? It is used in voltage calculations here."
in closed loop designs you call beta the feedback factor, and call (A * Beta) your loop gain. your A and Beta can be used to determine the accuracy of your closed loop amplifier. Normally designers refer to AB instead of just A since A can be impacted by the closed loop the amplifier is placed in. I actually have A&H so a page or chapter reference would be good...I dont use this book too much I reference gray and meyer more often.
-Pb
ps sorry for any misleading confusion heh

I'm dealing solely with CMOS design here, not BJTs. The equation I'm referring to is on page 271 of the 2nd edition, 6.3-15.
In this design however I think I'm only dealing with the open-loop specifications, so don't know how I could determine anything about the feedback factor?

I told you before it is not related to the bipolar not to a closed loop feedback factor. you still working with open loop CMOS Op-amp. the beta here is the technology parameter , sometimes people give it the name Kp or Kn depending on the MOS type. K= K'.(W/L), K' is given by your technology.

I suggest you please before you go in to the design you must read from the first chapter in order to know how this came . it is not right thing that you only follow the procedure directly. because after you finish the circuit may not work, and in order to fix it you must know the theory behind it. Keep a time for your project, read good then work.
if you have any question please ask me

cork-spotters said:

I'm dealing solely with CMOS design here, not BJTs. The equation I'm referring to is on page 271 of the 2nd edition, 6.3-15.
In this design however I think I'm only dealing with the open-loop specifications, so don't know how I could determine anything about the feedback factor?

Click to expand...

I agree with Junus, I saw the reference in the equation it is not a constant or a globally used Beta, it is a shorthand variable to equal the un*cox*w/l, I do not use this notation but I have in my college days used k'. so just replace Beta with u*cox*w/l.
a tip: if you come across an equation that uses a variable you do not recognize, refer to an example where they use the equation and see what they substitute in for the variable.
-Pb

Thanks again guys. I've never before seen it referred to as Beta either but at least now I know that it is referring to K.

In the A&H design process he also assumes we know the small signal gain of the pmos transistor M3 that's configured as a current mirror with M4. However this transconductance hasn't been calculated already in the procedure. I know gm = 2*Id/(Vgs - Vth) but we don't know Vgs in this case?

Hello cork

Change the relationship in to current, gm = (2*I*K'*(W/L))pow(0.5)

cork-spotters said:

Thanks again guys. I've never before seen it referred to as Beta either but at least now I know that it is referring to K.

In the A&H design process he also assumes we know the small signal gain of the pmos transistor M3 that's configured as a current mirror with M4. However this transconductance hasn't been calculated already in the procedure. I know gm = 2*Id/(Vgs - Vth) but we don't know Vgs in this case?

Click to expand...

Ok, I think I'm nearly there. I need to verify my open loop gain however, and this requires lambda of the process which I don't think I have?
These are the process parameters I've been using: **broken link removed**