Designing a 4-bit non-sequential synchronous counter

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JJBladester

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I am working on a 16:4 MUX that is comprised of four cascaded 4:1 MUXs. Each MUX has an active-low enable pin. To enable one MUX at a time, I need to use a counter that outputs the following:

Clock Cycle 1: 1110
Clock Cycle 2: 1101
Clock Cycle 3: 1011
Clock Cycle 4: 0111

In decimal, the clock is counting from 14 to 13 to 11 to 7 and then repeating.

I've generated a state diagram, a next-state table, a J-K FF transition table, the appropriate K-maps based on these tables, and finally a set of minimized SOP expressions from the K-maps. However, my output pins (Q0, Q1, Q2, and Q3) are all high all the time. I don't understand why.

**broken link removed**

My tables, K-Maps and SOP expressions are here: **broken link removed**
 

What are the status of the Clr and preset inputs if they are not proper the ops will always be 1 irrespective of the inputs
 

my output pins (Q0, Q1, Q2, and Q3) are all high all the time. I don't understand why.

I don't see where you initialize the 1st state (1110). It could be any state.
 

What are the status of the Clr and preset inputs?

**broken link removed**

I have the active-low ~CLR pin set high.

This is the output I get. The Q outputs of all four J-K flip-flops are low until the first positive clock transition at which point they go high and stay high.

**broken link removed**
 
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I think the last Preset and the clear pins are causing havoc in your design do rectify them to remove your trouble

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There is some error in the design part

each ff has J=1 and k=~Qn-1

IF so the input combination in all the cases are 10 in the JK and the corresponding ops are Qn=1 and ~QN=0
 

The 74107N J-K flip-flops I'm using don't have a SET pin. From the logic analyzer output I included in my previous update, you can see that all outputs are initially 0. MultiSim, the software I'm using, has 74109N J-K flip-flops with active-low ~PRE (preset) pins. How do I push an initial value to those pins once and then keep them high for the remainder of the circuit operation? Would a set of one-shot's work?

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There is some error in the design part

Each FF has J=1 and k=~Qn-1 so the input combination in all the cases are 10 in the JK and the corresponding ops are Qn=1 and ~QN=0

I must be making an incorrect assumption when grouping cells on my Karnaugh maps, then. I've gone over them more than a handful of times and the 0's, X's, and 1's are in the correct places. Specifically for my J0, J1, J2, and J3 maps... Is it correct that I am grouping all cells on those map to make all J inputs equal 1?
 
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Just keep the preset pin high through out the operation that should solve your issue I guess

The K maps are fine to the best of my knowledge
 

MultiSim, the software I'm using, has 74109N J-K flip-flops with active-low ~PRE (preset) pins.
74109 FFs work differently than 74107 FFs: the former have ~K (i.e. inverted K) inputs.

How do I push an initial value to those pins once and then keep them high for the remainder of the circuit operation?
Use an appropriate pulse source (initial value longer than the 1st active clock edge).
 

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