Designing 16 bit uP in VHDL

[LLCD]

all,

I am a newbie when it comes to making a clone of an old 16 bit uP
in VHDL. I know there are a lot of gurus around here so here
is my question.
I am looking for a feedback or hindsight on what to expect
when undertaking such a project. Are there any good books written
which might help me in tackling this kind of problem?
I know that testing this model will probably be one of the hardest
thing to do.
Thanks,

LLCD

 

[dainis]

Look at:
h**p://users.easystreet.com/mbutts/xr16vx_jhdl.html
h**p://www.fokus.gmd.de/linux/HOWTO/CPU-Design-HOWTO-4.html
h**p://www.opencores.org/projects/
h**p://www.fpgacpu.org/

 

[jimjim2k]

Hi

Look deeply at this URL:

1. h**p://tech-www.informatik.uni-hamburg.de/vhdl/

* -> t

tnx

 

[LLCD]

Thanks.

Thanks for the links!

LLCD

 

[goodboy_pl]

VHDL book with a cpu design example...

Dear friend,
if u r looking for a good book for learning VHDL along with designing a complete cpu, take a look at:

https://www.cs.ioc.ee/yik/lib/21/Navabi1.html

the book is:

VHDL: ANALYSIS AND MODELING OF DIGITAL SYSTEMS
Zainalabedin NAVABI, Northeastern University
Series: McGraw-Hill Series in Electrical and Computer Engineering
ISBN: 0-07-046472-3

also i think testing a ready to use(and also small !) core from opencores site is very good for better learning:

www.opencores.org

 

[arrow]

you can check the attached, really I did nor read it yet but it my help