u24c02
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Hi.
I have some questions about full chip level verification methods with cpu.
I am trying to implement full chip level for design verification with cortex M3 series.
Now I have almost got files to implementation like as cm3, bus, memories..
As I know these each items are already verified by ARM or tech companies.
But the problems are they each have configuration each by componants. It's meant each items have verification code by itself. But the problems are if they are combined. How can I verify combined DB?
1.so I want to ask you how do you verify bus itself?
2.How do you verify bus with memories?
3.How do you verify cpu with bus?
4.How do you verify cpu with bus and memories?
p.s )
is there any method to verify BUS matrix? Or BUS?
I have some questions about full chip level verification methods with cpu.
I am trying to implement full chip level for design verification with cortex M3 series.
Now I have almost got files to implementation like as cm3, bus, memories..
As I know these each items are already verified by ARM or tech companies.
But the problems are they each have configuration each by componants. It's meant each items have verification code by itself. But the problems are if they are combined. How can I verify combined DB?
1.so I want to ask you how do you verify bus itself?
2.How do you verify bus with memories?
3.How do you verify cpu with bus?
4.How do you verify cpu with bus and memories?
p.s )
is there any method to verify BUS matrix? Or BUS?