Design UVLO (Under Voltage LockOut) in DC-DC Converter?

[shaq]

uvlo design

Dear all,

Anyone has the idea on designing UVLO circuit in DC-DC converter?

If I want to design 2.2v of UVLO with 50mv hysteresis, how should I start?

 

[ljy4468]

design uvlo circuit

In my case. I just use hysteresis comparator.
Vref is 2.2V, 2.15V.

and comparator output connects to output diasble pin.

 

[bicave]

circuit under voltage lockout

Basically UVLO is a simple comparator, Input voltage divide by R then compare with Vref. By adjust resistor value you will have 50mV hysteresis.

 

[shaq]

uvlo comparator

Basically UVLO is a simple comparator, Input voltage divide by R then compare with Vref. By adjust resistor value you will have 50mV hysteresis.

I think using R-string to generate voltage is needed more current consumption.
(unless super large resistor, i.e. Mohm order)