Design Question use Ap0ll0

[hytsq]

When I use Ap0lll0 to Design my Circuit , I meet These questions:

Timing graph cleared.
#(xdb_copy.c: 1078) Net VDD with no sink (1 times)
#(xdb_misc.c: 644) xdb_fill_port_position() port 'div' no pin found (7 times)

DRC Brief Error Summary
Error Type Num Description
Met1 Spacing 100 metal1 minimum spacing = 0.6

Begin global routing.
........
...............
**** WARNING:Ignore 9 top-cell ports with no pins!

How to sovle these 3 question?

 

[bkat]

i meet the same problem,
who can deal with this problem??