design problems in 74ls74 by verilog

[MRFGUY]

74ls74

Hi,

I just start to learn HDL and choose to study verilog. I try to write D-FF (74ls74), but it shows some errors. I've seen some D-FF example but those did not include preset and clear.

What wrong with my program? Please help me. Thanks alot.

Following is my program by using Xilinx

module dffpc(d, q, preset, clear, clk);
input d, preset, clear, clk;
output q;
reg q;

always @ (posedge clk or posedge clear or posedge preset)
begin
if (preset)
begin
if(clear)
q<=d;
else
q<=0;
end
else q<=1;
end

endmodule

ERRORS:

WARNING:Xst:1467 - dffpc.v line 11: Reset or set value is not constant in <q>. It could involve simulation mismatches
ERROR:Xst:899 - dffpc.v line 11: The logic for <q> does not match a known FF or Latch template.

 

[nand_gates]

xst:1467

You need to modify ur code as follows...
Both asyncronous set and reset are to be handled this way...
Here in this code preset has priority over reset...

module dffpc(d, q, preset, clear, clk);
   input d, preset, clear, clk;
   output      q;
   reg         q;
   
   always @ (posedge clk or posedge clear or posedge preset)
     begin
         if (preset)
           q <= 1;
         else if (clear)
           q <= 0;
         else
           q <= d;
     end
endmodule // dffpc

Hope this helps