Design PCB for LAN PHY (STM32F4x7 + LAN8742A)

I want to use on a two-layer board STM32F4x7 and LAN PHY LAN8742A , unfortunately I have no experience with PCB design for PHY and I have not found a exmples for it.

1. Digital part RMII
How must the signals tracks be the same length?
I think,for a 50MHz bus this idifferences in length in the order of tens of mm do not matters not critical.

2.Output TX+,TX-, RX+, RX- to be 100 Ohm differentoal pair.
OK, I have problem.
I would like to make do with 2 side FR4 PCB.
On this PCB have 100Ohm Routes approx 0,65mm.
I want to use HR911105A LAN connector with integrated magnetick but this parts have on Pin 1 TX+ an on Pin 2 TX-, unfortunately LAN8742A
has them cross, TX+ on pin 21 and TX- on pin 20.
What with this?
I assume the pins TX+ and TX+ pn magnetics are not swappable?

I think you're just asking for trouble using a 2 layer board. Unless you can make your entire bottom layer ground plane, which you probably can't, you're going to spend most of your time trying to debug a poorly designed board.

I presume it's possible to make the PHY work on two-layer PCB, but most likely the design can't comply with EMI regulations.

One picture over a thousand words
The ground does not come out only in 3 places under TX RX pair
Please be forgiving, it's an unfinished draft.

Hi,

first of all: I don´t expect problems. .. because the traces are short.

But from the HF view:
I don´t think that the traces give a clean 100 Ohms differential pair. They need to be more symmetrical, they need more symmetrical neighbouring signals and they need an uninterrupted GND plane.
Did you calcuate the width for a 100 Ohms differential pair? They look too wide for my taste - but maybe they are O.K.

Klaus

The relatively large width is given by the height of the dielectric for a two-layer PCB .
I use Saturn PCB Design Toolkit and her is results for 0,65 and 0,75mm, on PCB is 0,65mm.
otherwise thank you for calming down, I was a little scared of madness, see for example her

If you analyze the connection between PHY and transformer as transmission line, then the termination resistors have to be placed on the PHY side.

Not sure where you got the suggestions to place 10 pF capacitors at the ethernet nodes, I guess from an EMI application note. But to have any effect, they must not be connected through lengthy traces as in your layout.

Rule of thumb says, traces shorter than 1/10 of wavelength can be analyzes as lumped elements (inductors or capacitors respectively). Respectively using thinner traces than nominal 100 ohm width between PHY and transformer adds quite a bit of series inductance, no big problem.