design op-amp in switch mode power supply

[huangjw]

hi,
i want to design a op-amp as error amplifier in step-down dc-dc switch mode power supply .whitch one should I consider more,gain, noise rejection, power rejection, bandwidth, output wing,common mode input.
or is there any paper?
thanks.

 

[Btrend]

u got the points.
but three more things u should take care is (1) clamping after OP's output, (2) lower output impedance (3) low offset
(3):lower offset will make ur output more accurate
(2):cause the output of OP is generally compared with a sawtooth waveform, u don't want ur OP's output disturbed by any kick-back noise or feedthrough noise from the comparator.
(1):and u will always limit (clamping) the op's output such that it will not go too far beyond the amplitude of sawtooth waveform.

 

[huangjw]

(2) lower output impedance
this iterm, I Think amplifier will be with capacitance load, the amplifier is always ota, so is its output impedance reasonable to be low?
(3) low offset : the objective is to accurately control POWER loop,right?
(1) clamping after OP's output: the mean is to clamp the output swing,right?

 

[huangjw]

u got the points.
(2):cause the output of OP is generally compared with a sawtooth waveform, u don't want ur OP's output disturbed by any kick-back noise or feedthrough noise from the comparator.

brend,thank you,but i don't know the relation between impetance and noise disturb?

 

[Btrend]

there is a very simple model for this.
imaging u have a noise source with output impedance Zs, and there is a point , say Vo, which u should take care, and the impedance at Vo is Zo. Then from the basic theorem , u will find the response Vo/Vs=Zo/(Zo+Zs). so Zo increase ==> Vo increase, Zo decrease ==> Vo decrease.
hope this helps

 

[huangjw]

3x, is there any paper about it