Design of Power Clamp

power clamp

0.18μm CMOS DIGITAL/ANALOG/RF TECHNOLOGY
TOPOLOGICAL AND RELIABILITY
DESIGN RULES
NOV 2008

Power clamp provides a discharge path between Vdd and ground during ESD event and is
normally off at all other times. Power clamp has been demonstrated in 0.18 um process using
RC-triggered NFET clamp. The clamp has a discharge NFET device, 400/0.4 um, that is
controlled by three inverter stages. The input of the first inverter stage is a RC network (set to
a time constant of ~1.5us). The inverters have been sized to reduce the switching threshold to
reduce the requirement of large R and C. Resistance R is realized by a long channel PMOS.
Capacitance C is realized by NMOS capacitor. This architecture of power clamp is proven in
silicon in 0.18 um technology and it can withstand 1.3A TLP current (equivalent to 2 kV
HBM ESD threshold). Impedance of power clamp at 1.3A is ~3 ohm. Lower impedance can
be realized using wider FETs and smaller silicide block length.



Resistance R is realized by a long channel PMOS.
Capacitance C is realized by NMOS capacitor.
Dose anybody know how to chose the PMOS and nmos?
thanks!!!

esd power clamp

The Nmos capacitor will be the gate oxide cap. So, if you know your unit capacitance for the nmos cap (listed in the design manual), you can size your nmos transistor to get the capacitance you want. For e.g. you can choose it to be around 1-2 pF depending on how much are it consumes.

the Pmos (long channel) active load this is what i would do:

During an ESD event the cap acts like a short and hence the vds across the pmos transistor changes with its source being close to gnd and its drain going up with the ESD pulse applied on vdd.
Since your are going to use the pmos as an active load, you'd have to rely on simulation to size the pmos. you would have to model the trace capacitance (and not so much resistance) at the drain of the pmos transistor because the ESD even is a 'high frequency' event. Since we are talking about sharp rises on Vdd and lower than 1.5usec, you'd have to pulse vdd faster than 1.5usec and make sure that the nmos output transistor turns on at that speed. At rise times > 1.5usec you want to make sure that the nmos output transistor doesnt turn on.
AFter you reach a final W/L for Pmos you can check if your values are right by simulating the resistor (pmos) and capacitor (nmos) separately and back calculating the R value for pmos and C value for the capacitance and making sure they give a RC time const of about 1.5usec.

I hope you are keeping in mind that since you'll need several parallel power clamps in your chip, you'd have to take into account the total capacitance and resistance.

rc triggered power clamp

transbrother,
thanks!
Do you have the circuits of pad, scrible line, esd for chart18rf?

why power clamp

mustangyhz,

I dont have these things sorry bro.