Design of Legacy chips

[garimella]

This is a curious question. Why no one is designing open source GAL, PAL or PLA? And no one has ever ventured into open source FPGA? What are the challenges? Would it be even possible?

 

[KlausST]

Hi,

I guess I don´t understand.
What "source" do you expect to be "open" .. that not already is open?

In what language do you expect the sources to be?
And what is the use of it?

Please explain.

Klaus

 

[andre_luis]

Why no one is designing open source GAL, PAL or PLA?

Are you looking to design in the ASIC scope the fabric of an FPGA/PAL in a more efficient/cheap way than the manufacturers' design houses do? If it's for fun, ok, but if you want something usable, it involves much more than just using standard cells. There's a whole engineering behind it, from the placement/layout of the circuitry up to the tool itself; not for kids.

 

[danadakk]

Of course the legacy parts largely were fabed in legacy processes, so an additional
challenge to insure device behavior/specs same, if purpose is replacement.

PALs and GALs, there are some modern process/architecture FPGA to handle that,
eg. small logic designs. Even mixed signal with ability to create custom logic/
functions using simple schematic capture and/or Verilog. An example of such a
device (one chip, many resources shown multiples onchip) :

This above standard lib expanded by users doing Verilog/Schematic capture and creating
additional onchip components. Like 24 and 32 but DDS, 74HC style logic elements, CORDIC,
CPLD.....

Users have created single chip oscilloscope with this part, some work I did (64 bit shift register, 64 bit counter) and :

Test Bed DDS and WaveDAC burst tool

Occasionally I need to generate custom wave forms and burst a known number of cycles into a DUT. This is a single chip solution, board I typically I use is $ 10. You just drag and drop components onto schematic, wire internally with a wire wizard tool and out to pins, right click and config...

www.edaboard.com

Regards Dana.

 

[dick_freebird]

It's likely that the smallest modern FPGA is priced less than a "vintage" PAL. Just by volume economics.

Likely any present PAL will be ASIC-ized along with all other doable content on the next board spin, as BOM reviews would likely call out multiple EOL threats in any legacy board (it's ugly out there).

I've thought about doing exactly this but find no real traction at present or past, and see no future that something better won't cover.