design of edge detection circuit

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subbareddy443

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hi eny one help me to design a positive edge or negative edge detection circuit
 

What did you start with?
 

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If the signal you want to detect is slower than the main clock, you can use 3 flip-flop in series to get 3 samples of the input and detect the edge by detecting the "100" value (or "110").

d1 <= INPUT;
d2 <= d1;
d3 <= d2;
edge = d1 & !d2 & !d3

You can also detect falling edge the same way. This kind of circuit is used for example in I2C logic to detect the edge on SCL or SDA.
 

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To haykp >
I'm sorry but I don't have a link to a reference with the circuit so I wrote a simple schematic.

Regards.
 

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Code:
Although not obvious at first sight, the suggested logic is still succeptible to metastability, which can result in missing an edge. You should better refer to the standard solution from text books:
Code: 
edge = d2 & !d3
It's however not necessarily required to register the edge bit before processing it.

P.S.: On the other hand, if we assume, that a single FF is sufficient to defeat metastability and connect d1 and d2, what's the purpose of d3? Maybe I missed a feature of your code.
 
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Hi FvM,
You are right, there is a risk of metastability. But I would say that it is almost always the case when trying to sample external data.
Using several FF in series with no logic in the middle can help avoid metastability (care is needed during P&R).
As for using 3 FF, it's to make sure glitch are not detected as an edge. Of course the size of the glitch that can be avoided depends on the clock speed.
This circuit can not be used in all case, but is OK for simple case.
 

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try searching testbench.in or asic-world.com
 

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Is input signal which has to be detected is synchronous to destination domain ?
 

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