design of current steering DAC with CMOS

[aroma658]

Hi freinds,

I m a new member of this forum and wud like to thanx the moderator for starting such a good forum for budding designers like us.
i need some guidance and suggestions as how to design a N+1 CMOS current steerig DAC which consists of current mirror at its input and its has an opamp with resistance feed back . Also how to find the number of bits that the converter can have while being monotonic .

also how to find the converter settling time if it changes from one set to of bit to others. for example 0110 to 1000

plz gudie with few text or books from where i can clear my fundas because i feel when i read the theory then i feel i can solve the design but when it comes to applicaton i m stuck at few minor places.
can somebody plz tell which book i shud follow which has no of solved numerical designing problems so that i can clear my concepts.
hoping for a positive reply

 

[Analog_starter]

Hi,

For the circuit, it is not complex when =< 10bits.
I think you must carefully layout, match, match and match.

Best Regards
Analog_starter

 

[yibinhsieh]

here is one thesis for current DAC from berkeley.

 

[yen]

I am doing about current matrix(current steering digital to analog).
I need to permute my current matrix.
How can my permutation style get good INL and DNL?
Thank you.

 

[Analog_starter]

You can use Random walk permutation style, but it is difficult to implement decoder and floorplanning.

Best Regards
Analog_starter

 

[aroma658]

Hiiiii yibinhsieh


can u plz send me the link for teh thesis on current steering DAC of berkeley

 

[bastos4321]

Look at the papers from KUL. They are very strong in this area.

Bastos

 

[aroma658]

"Look at the papers from KUL. They are very strong in this area"


hi bastos

thanx for the reply can u plz elaborate more on which kul paper i can see or plz kindly send me some link




aroma

 

[bastos4321]

"Look at the papers from KUL. They are very strong in this area"


hi bastos

thanx for the reply can u plz elaborate more on which kul paper i can see or plz kindly send me some link

aroma

Some references:

J. Bastos et al., “A 12 bit Intrinsic Accuracy High Speed CMOS DAC”, IEEE Journal of Solid State Circuits, Vol. 33, No.12, pp. 1959-1969, December 1998.

Anne Van den Bosch et al. “An Accurate Statistical Yield Model for CMOS Current-Steering D/A Converts”, IEEE International Symposium on Circuits and Systems, Vol. IV pp. 105-108, Geneva May 2000.

Anne Van den Bosch et al. “A 10-bit 1-Gsample/s Nyquist Current-Steering CMOS D/A Converter”, IEEE Journal of Solid State Circuits, Vol. 36, No. 3, pp. 315-323, March 2001.

Peter Kinget and Michiel Steyaert, “Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits”, IEEE Custom Integrated Circuits Conference, pp. 333-336, 1996.

Geert A. M. Van der Plas et al, “A 14-bit Intrinsic Accuracy Q2 Random Walk CMOS DAC”, IEEE Journal of Solid State Circuits, Vol. 34, No. 12, pp. 1708-1718, December 1999

Bastos

 

[yibinhsieh]

Hiiiii yibinhsieh


can u plz send me the link for teh thesis on current steering DAC of berkeley

Sorry! Because i got it many years ago. So I didn't remember it!

Yibin.

 

[opamp741]

Here is the link dude..
**broken link removed**