design of ASIC CMOS opamp

[carporsche]

cmos op amp design

Hi

I am designing an application specific CMOS op-amp which has very stringent requirements.
I am starting with a basic 2-stage topology
Some of the requirements would be :
1. Unity gain Bandwidth > 500MHz (Also in feedback my opamp needs to have a 3dB Bandwidth of > 25MHz)
2. High gain >75dB
3. Another very important requirement of my design is tht the biasing of my op-amp is independent of the feedback circuitry .
4. I am using Vdd = 3.3 V and Vss = -3.3 V (0.6 um tech). If i maintain my input common mode level at 0V i need my output dc level to be at 0V too.

I would really appreciate if any of you could provide me any inputs on these.

thanks

 

[karanjain]

cmos opamp design

Hi

Is there any slew rate requirement as well and max current allowed?

other wise take current to be 5ua , Coupling capacitor (Cc)= 1pf
then
wgb(unity gain band width )(500 meghz) =
gm(or transconductance gain of diffpair)/Cc ;

(w/l) ratio of the second stage should be 2 of the mirror of the 1st stage.
this will some what give better offset voltage

now gain ----- you know transconductance gain of 1st stage multiply it with output resistance.
now remaining gain will come from second stage.
gain= gm*rout(of 2nd stage)
gm of second stage is easy to compute = 2*I/ Vov
Vov = Vgs of mirror of diff pair - Vth of mos

hope it might solve your problem.

 

[edge_tv]

cmos opamp

Don’t use a two stage approach; you will burn too much current in the second stage.
Unity Gain Bandwidth = 500 MHz => for stability second pole should be around 1.5 GHz!!!!!
Second Pole = gm(second stage)/(2*pi*Cload), believe me that will cost current.
Normally a folded cascade should be enough to reach 75 dB, but probably not with that speed. You have to look into your process, could be that you have to do gain boosting.