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design of 8 bit shift register in cadence virtuoso

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tisheebird

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Hello everyone.

I have to design a 8 bit Shift register in cadence virtuoso by using bus. I have made 1 bit SR and now planning to simulate the same 8 bit SR with same 1-bit SR. I don't need to cascade 8 1-bit SR.

Just one time and it should automatically repeat.


Please tell me with the steps:


Cheers.
 

If you have a single bit shift register SR:

8-bit-shift_register.png

The connectivity results from the io signal's bit order inherently.
 

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