design of 1.5bit/stage ADC - Verilog-A

Status
Not open for further replies.

lemon_miin

Newbie
Joined
Sep 15, 2021
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
25
Hi All.
I want to design a 1.5bit/stage pipeline ADC.
I saw one example coding from the website (as below) and had query.

Is anyone know why vout= ((V(vin)- 0.9)*2) - 1 ?

Code:
//part of coding
@(cross(V(ph2)- clk_vth , +1)) begin
if (dd1 > 0.9)
begin
vout = ((V(vin)-0.9) * 2) - 1;
end

else if (dd0 > 0.9) begin
vout= (V(vin) - 0.9) * 2;
end

else begin
vout= ((V(vin) - 0.9) * 2) + 1;

[moderator action: added CODE tags]
 
Last edited by a moderator:

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…