design of 1.5bit/stage ADC - Verilog-A

[lemon_miin]

Hi All.
I want to design a 1.5bit/stage pipeline ADC.
I saw one example coding from the website (as below) and had query.

Is anyone know why vout= ((V(vin)- 0.9)*2) - 1 ?

//part of coding
@(cross(V(ph2)- clk_vth , +1)) begin
if (dd1 > 0.9)
begin
vout = ((V(vin)-0.9) * 2) - 1;
end

else if (dd0 > 0.9) begin
vout= (V(vin) - 0.9) * 2;
end

else begin
vout= ((V(vin) - 0.9) * 2) + 1;

[moderator action: added CODE tags]

 

[sutapanaki]

Do you really expect an answer to that?