dili Neo
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Hi all,
I am trying to design a D flip flop using TSPC . I am using this architecture: https://upload.wikimedia.org/wikipe...e_edge-triggered_flip-flop_with_reset.svg.png
I want to know how to size the NMOS and PMOS. I am working in TSMC65nm. I am looking for a methodology on transistor sizing in TSPC. I am using a pulse of 180ns pulse width and time period 300ns as D input while clock is of time period 50ns.
Kindly help me with this.Thanks in advance
Cheers
I am trying to design a D flip flop using TSPC . I am using this architecture: https://upload.wikimedia.org/wikipe...e_edge-triggered_flip-flop_with_reset.svg.png
I want to know how to size the NMOS and PMOS. I am working in TSMC65nm. I am looking for a methodology on transistor sizing in TSPC. I am using a pulse of 180ns pulse width and time period 300ns as D input while clock is of time period 50ns.
Kindly help me with this.Thanks in advance
Cheers