Design methodologies

what are the different design methodologies cmos op-amp....?
Which one is preferred by designers and why........?
Thanx in advance............!

I think that an important design methodology is gm/Id. This methodology specifies a process or algorithm for solving an analog design problem.

It really depends on your problem, but typically the 1st decision is the amplifier topology, folded, 2stage, telescopic, etc. then when it comes to sizing devices and setting voltages, it comes to your specs, low noise means large devices, high current, typically in strong saturation. low power requires sub-threshold operation of input fets which requires vgs relations with vt. this is maintained through w/l and current.

I have found over my time that i choose an architecture, for me, my bread and butter is the folded. then i look at my requirements ( power, noise, signal range, loading, speed, accuracy) there are going to be trade offs between most of these. For example its easy to make a fast amp, but hard to make a fast amp with low noise driving a high cap at low power, thats because fast amp usually requires low caps, and low noise usually requires large sizings, which means more parasitic caps. so you compensate with more current but that means more power. Start with understanding which knobs you can use. Also make sure you do your spec sims at the extreme corners , vt changes with temp and so what might meet spec at room might die from devices getting squeezed out at one temp.

Thanx for your reply...
My question is not about choosing the topology of op-amp.
"My question is how to get W and L values of a specific schematic either it might be any op-amp or any thing else...
In other words if schematic is given (chosen depending on its requirements) how to get w and l values of each MOSFET.....?

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Thanx for your reply...
what are the other methodologies ....?
can u provide some material about gm/id methodology..?

thats a very long complex answer

but my other answer still applies. it starts off with you knowing your requirements. hich are the most important so you know what you can give in a little to.

I start off determining the bias current of the diff pair and their sizes (this sets the gm, which along with the parasitics(R,C) affects the gain, slew, and bandwidth pre-compensation)
then i design the 2nd stage or folded stage. again the W,Ls are picked(if folded these are basically the parasitics i referred to above). the sizes along with the current and gain determines the noise impacts, which could/will require revisiting the devices.
then I design the bias block and current mirrors and set the biased voltages, i usually keep about 100mV headroom margin on a device, this seems to be enough for performance across corners and temp (sims will be used here for this verification).
then i look at mismatch sims, along with corner sims to get an idea on its yield and make sizing improvements when needed, also keep in mind layout matching when sizing devices, you should avoid sizing devices to allow odd number of stripes.

I have on my board next to me a reminder of all my ota sims i try to run, might help you have insight into something i forgot to mention above
they are:
noise,matching, linearity, harmonics, settling, stability, and accuracy.

prestonee said:

thats a very long complex answer

but my other answer still applies. it starts off with you knowing your requirements. hich are the most important so you know what you can give in a little to.

I start off determining the bias current of the diff pair and their sizes (this sets the gm, which along with the parasitics(R,C) affects the gain, slew, and bandwidth pre-compensation)
then i design the 2nd stage or folded stage. again the W,Ls are picked(if folded these are basically the parasitics i referred to above). the sizes along with the current and gain determines the noise impacts, which could/will require revisiting the devices.
then I design the bias block and current mirrors and set the biased voltages, i usually keep about 100mV headroom margin on a device, this seems to be enough for performance across corners and temp (sims will be used here for this verification).
then i look at mismatch sims, along with corner sims to get an idea on its yield and make sizing improvements when needed, also keep in mind layout matching when sizing devices, you should avoid sizing devices to allow odd number of stripes.

I have on my board next to me a reminder of all my ota sims i try to run, might help you have insight into something i forgot to mention above
they are:
noise,matching, linearity, harmonics, settling, stability, and accuracy.

Click to expand...

Regarding different sizing methodologies, the one described here is based on symbolic methods. The designer has approximative formulas in his head that relate specs to parameters. It is taught in analog text books and design classes extensively. It is good for the student to understand the circuit. But it has drawbacks: it doesn't work well if specs depends on multiple parameters and there are many trade-offs between specs, because then you cannot size simply step-by-step but have to solve a nonlinear equation system. Approximative formulas can be developed easily for small-signal AC specs (gm, gds, ...) but can be very difficult to handle large signal transient specs, temperature dependency, process variation. This method is therefore most popular for small low frequency analog circuits. As described above, designers usually solve only for the easy specs and then simulate to verify the others and hope for the best. This does not produce the optimal solution. If you have a more complex topology with tight specs, multiple feedback loops, high gain stability issues, wide temperature range, then this method comes quickly to its limits and you end up with numerically tuning the circuit by running parameter sweeps iteratively. This is very inefficient when done manually. My company sells circuit sizing tools for this purpose, see www.muneda.com. This is a different methodology. The designer enters his rough approximative solution as a starting point, then the tool runs simulations and numerical optimization algorithms. The optimizer has to consider all kind of temperature variations, corners, mismatch statistics, plus a lot of circuit constraints (saturation, inversion, current symmetries, ...) plus parametrization (like: equal length for current mirrors), ... so it's not simply a Matlab optimizer + Spice. The main applications are complex analog circuits, RF design, high-speed I/O, memory interfaces, full-custom digital, standard cells.

Hello

please I have couple of questions to you

1. Please I would ask you about the value of the transistor headroom margin, you said you always set it to 100 mV, I have read in text books that this voltage effects the design performance , could you please explain me how ??

2. How you will assure that your design is going under the strong inversion ??

3. why the odd number of transistor fingers are not matching good ????

prestonee said:

thats a very long complex answer

but my other answer still applies. it starts off with you knowing your requirements. hich are the most important so you know what you can give in a little to.

I start off determining the bias current of the diff pair and their sizes (this sets the gm, which along with the parasitics(R,C) affects the gain, slew, and bandwidth pre-compensation)
then i design the 2nd stage or folded stage. again the W,Ls are picked(if folded these are basically the parasitics i referred to above). the sizes along with the current and gain determines the noise impacts, which could/will require revisiting the devices.
then I design the bias block and current mirrors and set the biased voltages, i usually keep about 100mV headroom margin on a device, this seems to be enough for performance across corners and temp (sims will be used here for this verification).
then i look at mismatch sims, along with corner sims to get an idea on its yield and make sizing improvements when needed, also keep in mind layout matching when sizing devices, you should avoid sizing devices to allow odd number of stripes.

I have on my board next to me a reminder of all my ota sims i try to run, might help you have insight into something i forgot to mention above
they are:
noise,matching, linearity, harmonics, settling, stability, and accuracy.

Click to expand...

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Ramakrishna_444 said:

what are the different design methodologies cmos op-amp....?
Which one is preferred by designers and why........?
Thanx in advance............!

Click to expand...

Please before starting the desing in the analog IC, you must read and understand the analog circuits like the op-amp and the biasing circuit from a text books. After that you will get the idea by yourself about how to design and beleive me you will make your own procedure. you reminded me with my self when first I started the Analog design, I asked exactly the same your question. Then I got the answer from the most amazing two books of analog design, these are

1. http://books.google.de/books?id=-crQYfNHJDUC&dq=cmos+analog+circuit+design&hl=en&sa=X&ei=E8z9UNSiKMTMtAaWtIH4BQ&redir_esc=y

2. http://books.google.de/books?id=uxFTAAAAMAAJ&dq=cmos%20analog%20circuit%20design&source=gbs_similarbooks

those two books give a design examples of different type op-amp.

the other 4 books that help I highly recommend you (specially Nr. 5, is considered as father of them)

3. http://www.amazon.com/Microelectronic-Circuits-Electrical-Computer-Engineering/dp/0195323033/ref=pd_rhf_se_s_cp_19_0MVC

4. http://books.google.de/books?id=rCxNKzuBIAwC&printsec=frontcover&dq=cmos+circuit+design+layout&hl=en&sa=X&ei=icz9UMzdNs_OswblyYCIDw&ved=0CDEQ6AEwAA#v=onepage&q=cmos%20circuit%20design%20layout&f=false

5. http://www.amazon.com/Analysis-Design-Integrated-Circuits-Edition/dp/0471321680

6. http://www.amazon.com/gp/product/0072380322/ref=pd_lpo_k2_dp_sr_2?pf_rd_p=1278548962&pf_rd_s=lpo-top-stripe-1&pf_rd_t=201&pf_rd_i=0471321680&pf_rd_m=ATVPDKIKX0DER&pf_rd_r=02YKFGT001R8X5YH2XS7

7. http://books.google.de/books?id=6-8j7ycydtcC&dq=analog+integrated+circuit+design%2BDavid+John&hl=en&sa=X&ei=itD9UN2ADofWsgb0wYCgAg&redir_esc=y

you need your time to cover the theory from these books, in the same time you must beleive that what you read is the simplified model of the actual devices so it will not go exactly practically.. however understanding the theory is very essential to make you verify your design during the simulation phase.

please read these books from the first page and never miss any topic, and dont wary, you will learn it as I did.
dont try to search for another books because these are the best books

I think first I should clarify there are two headrooms per gate, vgs-vt and vds - (vgs-vt). for cascode devices on the output i typically try to allow about 100mV of headroom for vds - (vgs-vt), too much headroom and you are throwing away signal swing, too little headroom and you run the risk of squeezing out your cascodes, and i use 100mV as a minimum for current mirrors. as for vgs - vt i also work around 100mv for strong saturation. and around -100mV for subthreshold operation( i may go over the 100mV for saturation, but i use -100mV as the abs max for subth). calculating your vgs-vt is straight forward, and some would probably say calculating your vds is as well, but i tend to run a simulation to see where these numbers are, guess i kind go based on my experience a bit here. Vds will have some effects, i contribute most of these from the channel shortening effect(the 1+Lambda * VDS ) term. which is why you want to make sure accurate circuits that are a diff pair or current mirror share near exact vds as well as vgs. a mirror whos vds is different will have slightly different current, which also affects gm. odd number of devices is a no no because of the difficulty to lay out. when you layout devices you have the layout engineer do so in pairs, that away the drains can be shared and that leaves the sources to connect to other devices, sharing the same active. like the current mirror across the amp, if you have poor layout your well designed diff pair could start off with a current imbalance, which leads to offset. for example say you have bias current going to an amps pfet, then that pfet mirrors say 5 times, 1 mirror for the diff pair, 2 mirror for the folded cascode outputs, 1 for the lower cascode bias, 1 for the higher casocde bias. say this is a high gain low noise design, you will likely be mirroring large currents, so your mirrors might be sized to something like effective w/l of 100/1 which you would make up with say 10 10/1's for simplicity lets say your current branches are 5,20,10,10,5,5
how would you lay this out? the 3 5's have an odd number meaning on 1 side is a drain , the other is a source, so you cant share actives between all, but if you change it to 4,20,10,10,4,4 you could easily lay this out in a shared active. its good to keep the layout issues in mind when designing, if you give the layout engineer a non symmetric layout, you cant complain about mismatched parasitics etc.

-Pb
If others have disagreement feel free to chirp in. there's always room to learn something new , oh and the 100mV rule of thumb I use is directed for my current temperature range process, and allowable performance. this is something you must verify with your worse case sims and compared to your specs.