Design issues in 1.5b plpelin A/D converter

[Tahar]

Hi Guys,


My questions are about the design of one stage of (1.5b/stage plpeline A/D converter )

Here are the specifications:

a/ Technology 0.18 um CMOS UMC
b /Supply voltage 1.8 V
c /1.5 bit stage
d /Maximum sampling rate 20 MS/s
e /Differential Input range 1Vppd[/u]

This stage is tradionnaly implemented according to the attached picture.

You see that the main building block of this design are sub-ADC, sub-DAC,gain and sample hold circuit.


Could you suggest me some sub-ADC and sub-DAC, gain and sample hold, structure for the particular requirement of this project (b/) and (d/),

Thank u in advance,

 

[totoro]

why not refer to some paper or thesis?
the resolution you have not mentioned is a key consideration of choosing pipelined architecture.

 

[Tahar]

Well if there is a thesis or a paper for the specific specification, no pb.

Now regarding the resolution, it is expected 4 stages that should reach a 10 bit resolution.

However, if only one stage is required and we know that we need 1.5 bit/stage....what could be the matter of talking in terms of overall resolution ?


(I am a beginner in this field, dont be surprised if u see beginner mistakes)

 

[nxing]

check some thesises from berkeley and you will find some one quite helpful.

 

[ezt]

Hi.
There are another very useful thesis beside Berkeley. find HUT (Helsinky University of Technology) website. there you can find interesting information about pipeline ADC design especially in Waltari thesis.

Regards,
EZT

 

[MLR67]

Hi ,
EZT you are right .
You will be able to find the ADC thesis at this URL:http://lib.tkk.fi/Diss/2002/isbn9512259087/
and other ones.

 

[opamp741]

Sub ADC : 3b Flash ADC
Sub DAC + Gain : Switched Cap Amplifier + Adder + Subtartctor
Amplifer for SH + Gain : Cascode amplifier with or woithout 2nd stage (depends on ur gain req)
Comparator for flash : Preamp followed by latch

ask me if u hav any doubt..

Added after 2 minutes:

here is a thesis for pipieline ADC.

Hope it will help you.


Yibin.

for more data on pipeline ADC go to
**broken link removed**

 

[tuza2000]

why you chose 20ms/s?

 

[manissri]

u can go for the umaine university and find the thesis of socklingum
umaine.edu/vlsi

 

[hubert008]

I think you should use two stage OTP.

 

[careking]

you can refer the Allen's book.

 

[kytan]

There are tons of papers on these kind of designs. For starters read all the mid 1990's berkeley thesis on pipeline ADC, at Paul Gray's website. Then search for all papers on low power low voltage design.
Important to think about resolution per stage, capacitor scaling, and whether you want SHA or not for low power design before you begin low level design

 

[yeziwong]

i think the key point is the OPA, and you should know the spec. of it, such as DC gain, GB,etc.

 

[aminmahdi]

hi
attachment file is "testing piplne analog to digital converter"

 

[yellff]

how many stage are you used? and how about your signal frequency and sampling
clock rate?