Design help in Verilog

[otis]

I have a state machine with few states. In one state the state machine sends signal to oscillator(or to analog block of the chip) to stop the clock.(for power saving)

After that the clock goes off(Oscillator will be stopped). it is valid for the whole digital block

Now there is no clock in digital domain. Then the state machine waits for external interrupt.

when there is a interrupt the state machine inform the analog blaock to start the clock. when clock received it should continue to the next state.

From my understanding it is not possible for the state machine to detect the external interrupt because there is no clock present.

So I guess I need some other simple external state machine or a combinational circuit to detect the interrupt and send signal to analog block. once clock restored then the state machine should start continue as usual.

could any one could give me an idea how to code this (syntheziable)? example code? concept?

Any input is highly appreciated.

Thanks in advance.

 

[jducluzeau]

here a link to FSM design guides from xilinx

**broken link removed**

 

[otis]

Thanks for the link.. But the tutorial does not deal with the issue that I have!

 

[jducluzeau]

Maybe you can consider your external interrupt as an asynchronous reset or smething like that and to code to the same way

 

[otis]

thanks for the input but it is bit complex. because it need to be glitch free!!!

 

[jducluzeau]

where does the external interrupt come? How is it generated?

 

[otis]

it comes form external world...from another chip(s)
It is not my interest that how it was generated

 

[FvM]

Why do you present a topic, that has been discussed in your previous thread in detail, as if it would be a new question? That's really annoying!

 

[otis]

Could be annoying..i agree...
I was tried the to implement the idea was given...But it did not fullfill my requirment.
So i wanted to get some fresh thinking...

Actually I wanted to give the link of old post. But if people see that post they will think in the same direction. that is why I did not mention the link!

Now the idea behind my belief is gone. But still I'm looking for new ideas...

Cheers!!!!

 

[beowulf]

Two ways:
1. Your async signal can bring the FSM out of reset
2. Another small dedicated cct that uses two flops. The input of F1 is connected to VCC, the output is connected to D of F2. The output of F2 is reset to your FSM that will bring it out of idle. The async reset is connected to the enable of both flops. This is a typical reset deassertion cct. It requires atleast two clk cycles before the rst is applied to the entire cct. If your async reset signal is a pulse, use a Latch with enable (no clk).
Would like to see more solutions

HTH,
Beo

 

[FvM]

But if people see that post they will think in the same direction. that is why I did not mention the link!

People, who seriously try to help will feel fooled, if the they realize, that basically the same answer has been given before. In my opinion, it's a violation of forum rule 3.0, unwanted cross-posts.

 

[skyfaye]

You people need to stop being jerks and help the guy out.

Ok, I'm will try to take a ***** at this problem.

Like one of the poster said, you can treat this interrupt similar to a reset.
I would assert this interrupt asychronously but deassert it synchronously.

Why assert it asynchronously?
Because there's no clock when the interrupt is asserted.

Why deassert it synchronously?
To avoid glitch. At this point, you already have a clock. To make your design clean, you should make sure your clock is stable (e.g. check PLL is locked) before deasserting the interrupt and using it in your FSM.

Hope it helps.

Regards,
Hung