design full address decoder 16kB(4kB)

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deepsetan

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if i want to design a full address decoder for 16kB RAM using 4kB SRAM,the total chips needed are 4..does it mean that the total chips needed for odd RAM is 2 and even RAM is 2?
 

This is usually done with a 74HC138 Decoder/demultiplexer. Each 4K ram gets the same LSBs of the address bus and the A,B and C inputs of the 138 gets the MSB of the address bus. The RAM chip selects are handled by the outputs of the 138.
Only 4 Rams are needed so you have two unused outputs of the 138.
 



this is the decoder i designed with base address $041000,how about the actual implementation?..should it be connected with 2 even RAM and 2 odd RAM(since it is 4 chips)?
 

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