Design for testability in ASIC/IC devlopment

[meet81193]

what is the difference between scan insertion and scan synthesis during inserting dft(desing for testbility) in my design? be as brief as possible?

 

[yuhiub90]

I think they are the same. Both refer to the process of replacing normal flops by scan flops of gate level netlist.

 

[meet81193]

No, I had consider that point but that isn't correct. They both are different. But how is the question?

 

[dpaul]

I also had the impression that both are the same. The tool replaces a normal FF, inserts a scan-FF and then produces a new netlist.

No, I had consider that point but that isn't correct. They both are different.

Can you please explain why that is not correct?

 

[meet81193]

Ya sure,
Now consider what is synthesis:
Synthesis = Translate + Optimize + Mapping
whats is insertion?
Insertion = Translate

 

[dpaul]

I thought we were talking about scan insertion and scan synthesis in particular. Not something in general.

 

[artmalik]

scan insertion is something which is an obsolete idea when the tools didn't handle scan during normal synthesis. One used to synthesize the Verilog netlist with non-scannable flops. then the flops were replaced by their scan versions (scan insertion)...and connect the scan_in,scan_en etc. This was older way of things. these days the tools take in scan-flops and do the optimization which is scan synthesis ( optimizing the scan chain also along with the logic). scan insertion is an older and obsolete concept.

 

[meet81193]

Thank you for your effort, it helped me.

can you please give an example of what optimization really happens? just an example which can clear my idea.

 

[artmalik]

one optimization is how the scan is stitched in such a way that the timing is met. You can connect scan chain for flop A-> B -> C or C->B->A.....one of them will be better for placement or timing. The tool optimizes for the placement and timing. logic optimization. ...suppose Q is connected to sin of the flop...you can as well use the logic after Q and take the signal which is derived from Q into the sin so that hold buffers are not added and you can use the logic itself to take care of the hold ...there are others but in simple terms scan is treated like any other signal and optimized....