Design for Testability for FPGA

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parthborda

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Hello,

Can you please give some highlights on following question related to DFT for FPGA?

1. Which EDA vendor supports DFT for FPGA?

2. What tools are available in market to do

- ATPG approach
- BIST approach

3. List out company who are using “DFT for FPGA”

4. What is industry recommendations to have DFT for FPGA in terms of process node(90nm, 45nm....etc)

Thank you in advance..:razz:
 

The one of the advantages of an FPGA is that the manufacturer can do a comprehensive test of all the logic at the factory so that the user doesn't have to repeat that testing.

You can have some insitu testing but you don't need all of the testing that an asic would have in it.
 


Thank you for your response.

So, is it mean we are not performing DFT during FPGA designing phase? if i am wrong than please correct me.
 

For the point 4, the customer could not know the node used for the FPGA.
DFT is technique to test the silicium built, the fpga has already succeded to DFT before to be sell by Xilin/Altera or other, you only need to used it.
If you made your own electronic board, is recommeded to have some tests to check the board himself, not the FPGA, boundary scan could help you.
 

I don't understand this.
FPGA-chip by itself is also a "chip". The only difference is that it's function feature is to be programmable. Therefore, I think FPGA chips must go through normal DFT/ATPG flow to ensure there is no manufacture issue. This is no different than normal ASIC chips of any functional features.
Of course, due to FPGA property, ATPG vector design might be easier than normal chips whose logic is not as cleanly "aligned" as FPGA does. But the DFT flow is indispensable.

Correct me if I'm wrong

Thanks
Leo
 

From what I've read in some older 4000 series Xilinx documentation the ATPG tests take advantage of the programmability of the FPGA and reprogram them with various configurations to test both the configuration logic and the core. I don't know about the latest generation of FPGAs with all the added hard IP. FPGA vendors must have some way of testing those blocks on a tester, but what it is I don't know.

Regards
 

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