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Design for test: Signature analyser

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jason_class

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Hi All Helpful Experts,

I would like to consult you about DFT I learnt in class last week(friday). I studied on saturday and today, but seems hard to understand at some point. I called students to meet to discuss but none of them agreed. SO I went to cyber cafe and scan my note(upload to geocities.com) and hopefully you can shed some light. This week lecture will be tougher, so I must grab the basics I supposed to know in last week lecture. Therefore I ask for your help to see my following enquiries.


On the page http://www.geocities.com/jason_class/masterslaveD.jpg
It is a typical master slave D-type circuit at bottom. On top, it is a circuit to analyse the signature on certain point by probing the node we wish for. In the picture, it is testing node PR for the D1 flipflop.


On the page http://www.geocities.com/jason_class/MSdfaultfree.jpg
we can see the signature labelled a each node. AM I right?


On page http://www.geocities.com/jason_class/Test.jpg.jpg
it shows all the intialise for PR, test for G1 G4 stuck at 1 and 0, Pr stuck at 0 , CLK stuck at 1 and 0. May I know how do we know all these ones and zeros are the test for these node stuck at one and zero

I learn before for a simple circuit . Lets say Xor for 2 input.
F= !A.B + A.!B //fault free
F= 0.B + 1.!B //A stuck at 1 case
=!B
For test A=0 B=1
F=1.1+0.0 =1
F'=!B=!1=0
Hence we can use A=0 and B=1 as a test for A stuck at 1 case.
This is simple case.
But for the master slave D type, may I know how to come up with table on page
http://www.geocities.com/jason_class/Test.jpg.jpg for all the stuck at. Please help me to understand.

Then May I know in order to test PR stuck at one for D1 flipflop, we should put a test "1" or "0" at PR and observe the output and why the reason.

On page http://www.geocities.com/jason_class/CRCsignatureG4dot8.jpg
shows all the siganture for node G4.8 which is the NAND output bfore D1 flipflop.
In this table shown, I would like to know how do we know when we should put a "o" at S input? In the table, it shows S is 0 , 0 , 0, then followed by 1, 1, (vertical down the table at column S). If we use different sequence of zero and ones, we will get different signature right? How do we do here?

On page http://www.geocities.com/jason_class/MSdfault.jpg
shows the same Master slave D type with a open circuit at connection between G3 and G4. Lecturer said it is a high for any open circuit. Do you know why is this so?
Then how do we get the CRC signature for this fault circuit? I do not know the S should start with what sequence of 0 and 1.
Please teach me
I beg you. I took time to scan and write this question neatly in hope you or any one who can help. I really beg you.


Hear form you
God bless you the kind soul

rgds and thanks
Jason the desparate
 

The idea behind testing is when you put something known at the input you expect something known at the output.Fig 8 gives you internal state of G4 when you vary input.Note internal state of G4 and compare with s input of test signature analyser on fig 9 same isn`t it.G4.9 is always high as your teacher says,and test sequence for that input you should make by yourself.Note that on fig 9 you have SHIFT REGISTER.
that`s all

ps. READ AGAIN ALL DIGITAL ELECTRONICS COURCE BOOKS
 

Dear All

Can anyone please help to explain using the example for fault free circuit. How to come up with the test vectors, polynomial for input tes vector, charaterics polynomial and the remainder based on the fault free circuit.
Then I will try myself to anaylse for the faulty circuit.
Please help .
Directing me to read all digital books is really something too general. Please give more hints.
Thank you


rgds and thanks
Jason
 

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