Design entry in Xilinx CORE Genreator

[Jack// ani]

Hi guys,

I'll be using Verilog for my top-level design entry. Wanted to know if there are any pros/cons selecting the Design Entry option as VHDL, instead of Verilog, as show below:

I know both the cores Verilog or VHDL will be functionally the same, just curious...

Thanks

 

[rberek]

The RTL code of the core you build will be built in VHDL then. If you don't mind, and are able to do mixed language simulation and synthesis, then you can leave it as VHDL. But if all of the rest of your design is in Verilog, there's not much point.

r.b.