[SOLVED] Design compiler weird behavior

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Jupiter_2900 said:
i changed my code to lower case , my problem is not with syntax error at all,
Click to expand...
I still don't know how you can claim there wasn't a problem. What simulation tool are you using, because Xilinx ISE/Vivado and Modelsim all complained with the mixed case IndexX and the indexX declarations not being the same. What ever simulation tool you are using must have problems with adhering to the Verilog LRM.

Given the poor track record of your simulator, I suspect it can't handle the mixed simulation of Verilog TB and VHDL netlist. Write out your netlist in Verilog and see if that fixes your problem.

If there is a problem with the VHDL instance in the Verilog then you should have been able to see that by examining the inputs/outputs in both parts of the hierarchy. You've never indicated if you've traced the source of the X's back to anything in the simulation, I've been assuming (probably wrongly) that you've tried this but couldn't determine why it went X. You could also try a small testcase design like a 4-bit case and see if you can't trace the X's back through that netlist. I understand a 256 case statement is a very large logic cone so it would be hard to trace back through the simulation of the netlist.

Unfortunately I probably make way too many assumptions on peoples debugging skills (I usually assume they are decent, and decent to me is probably excellent to most), so excuse me for not having made these suggestions (like a simpler testcase) originally.
 

dear ads-ee you are right, i just mistyped it, i was embarrassed , that is why i told you it is not anything with syntax error
 

Jupiter_2900 said:
dear ads-ee you are right, i just mistyped it, i was embarrassed , that is why i told you it is not anything with syntax error
Click to expand...
Why? I make typos all the time, and I've been writing Verilog/VHDL for decades.

Try some of the stuff in my previous post:
1) check top-level, lower level hierarchical signals in simulation on mixed simulation (assuming there are no binding warnings during elaboration of the simulation).
2) try a Verilog/Verilog TB/UUT simulation if the above indicates a problem with the interface between VHDL/Verilog.
3) try simpler testcase (mixed) and if it has same issue then trace the X's back through the logic to the source. As it should be a very small 4-bit case you should be able to put up all the signals in the netlist and just look for the first X in the simulation.

I've sort of listed these in what I perceive to be the least to most work (though arguably 1 & 2 could potentially be swapped)
 

i did all of these and i traced X back to output of lookup module (combinational logic) but i couldn't find out why ? all output nets of lookup have some valid values before end up to nana gates " because i used NandGateLibrary" , and question is what could possibly goes wrong in nand gates ?? and if lookup module has problem then why it works correctly when i post synthesis simulate it alone ??
 


I'm not sure where you traced back, you're not being entirely clear. I can't tell from the above description how far you traced back the X. Did you trace all the way through the hierarchy (if there still is any, don't know if your netlist is flattened or not) and down to a NAND gate that is producing an X with valid inputs?

If I wasn't clear you need to follow every X back through the design until you reach the first occurrence of an X or until you find something that is broken, i.e. A=1 and B=1 but A NAND B = X. In this hypothetical case it would mean the NAND gate model is busted.

You said "i did all of these" did all of what? The three points I made? What were the results? Give me information. I'm trying to help but you keep holding information back. I'm not sitting right next to you watching what you are doing!

I find this kind of behavior very very frustrating and am getting burnt out with participating on this forum.
 

hi
i came across something, i think my second design signal strength have been changed somehow and it is the cause for the problem , i have attach two picture of that are simulation results of module lookup alone ( the correct one) and simulation result of module lookup in second scenario ( when this module have placed beside the sequential module )
 

They are the same image, you didn't correctly post the first working one.

It also looks like the output out_port (I presume, since you didn't restrict the name to the signal name only) goes X because there are multiple drivers and one of them is always driving a 1.
 

hi
i came across something, i think my second design signal strength have been changed somehow and it is the cause for the problem , i have attach two picture of that are simulation results of module lookup alone ( the correct one) and simulation result of module lookup in second scenario ( when this module have placed beside the sequential module )
i think i should told DC somehow to add buffer between two modules in order to avoid this problem , but how can i do that ?

- - - Updated - - -

i attached both picture but it only shows one ???
 

I doubt it is a buffer problem, you have some static signal being applied to out_port that is resulting in X's due to multiple drivers.

The key is the fact that it only goes X when it tries to go low.

If this is the problem then you should have found this a long time ago with a simple search of the netlist and the testbench files to find everywhere out_port is connected. That's likely the first thing I would have done after seeing those waveform results. (see how a lack of information hinders the process)

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Oh, yeah. signal strength changes can hid these types of issues. One should never modify the default (hard) drive strength of VHDL/Verilog. You want to see X if multiple drivers are on the same signal driving to different values.
 

i get your point, but i did nothing wrong in my design, i don't have any multiple drive point in my design, i have checked design and these X are created at the end of lookup module after some nanagate (all nandgates inputs are correct and stable), then how it is possible ??

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ads-ee said:
Oh, yeah. signal strength changes can hid these types of issues. One should never modify the default (hard) drive strength of VHDL/Verilog. You want to see X if multiple drivers are on the same signal driving to different values.
Click to expand...

how can i prevent this signal strength changes ? i thought i should insert buffer in input of nand gates ?? but how can i do that ?
 

Basic debugging skills 101....isolate the problem.
Modify the netlist and change the name of one of those broken NAND gate outputs to a different wire/signal name and check if it still outputs an X in the simulation.

If it doesn't then there is something wrong with the port connection. I can't asses the likely hood of a wrong VHDL port type or maybe you let the tools insert I/O buffers into the sub modules. Don't know enough about DC to check if that might have happened in your script. You're the one with the netlist look at it and see what is connected to the output of the NAND gate.

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Jupiter_2900 said:
how can i prevent this signal strength changes ? i thought i should insert buffer in input of nand gates ?? but how can i do that ?
Click to expand...

We are talking about 9-value logic not buffers and physical signal strengths.

Things like weak 1 and weak 0, etc won't cause X's when driven by strong 0 and strong 1 respectively. I haven't seem models for gates that used anything but strong 0/1.
 

i see weird thing in netlist of top module
Code Verilog - [expand]
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assign intermediate[7] = N165;
  assign intermediate[6] = N269;
  assign intermediate[5] = N377;
  assign intermediate[4] = N471;
  assign intermediate[3] = N564;
  assign intermediate[2] = N641;
  assign intermediate[1] = N714;
  assign intermediate[0] = N778;
all of the N?? are output of first module (lookup) , actually output of nanagates and all are correct , and when it assign to output port of lookup module as shown above , it turn to x , why on the earth this could happen ??
 

So when N??? is not assigned to intermediate[7:0] the N???s output the correct data (no Xs)?
Are you sure there aren't any other assignments to intermediate, i.e. intermediate only shows up here and in the port declaration?

what happens if you change the netlist lines above to:
Code Verilog - [expand]
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assign intermediate[7] = 1'b0;
  assign intermediate[6] = 1'b0;
  assign intermediate[5] = 1'b0;
  assign intermediate[4] = 1'b0;
  assign intermediate[3] = 1'b0;
  assign intermediate[2] = 1'b0;
  assign intermediate[1] = 1'b0;
  assign intermediate[0] = 1'b0;

I expect all the bits of intermediate to go X if there is a problem with something driving it. Also try commenting all those lines out completely if intermediate does not go U then there is definitely something still driving a value onto it.
 
when we synthesis bottom-up approach , don't we expect each module just sit in upper module exactly ?? first code is synthesis of lookup in context of upper module :
Code Verilog - [expand]
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module lookup ( indexX, indexY, intermediate );
  input [3:0] indexX;
  input [3:0] indexY;
  output [7:0] intermediate;
  wire   n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
         n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
         n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
         n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
       ...
 
  NAND4_X2 U1 ( .A1(n86), .A2(n87), .A3(n88), .A4(n89), .ZN(intermediate[7])
         );
  NOR4_X2 U2 ( .A1(n90), .A2(n91), .A3(n92), .A4(n93), .ZN(n89) );
  OAI222_X2 U4 ( .A1(n101), .A2(n102), .B1(n103), .B2(n104), .C1(n105), .C2(
        n106), .ZN(n91) );
  AOI22_X2 U6 ( .A1(n2), .A2(n67), .B1(n71), .B2(n15), .ZN(n101) );
  OAI221_X2 U7 ( .B1(n108), .B2(n109), .C1(n110), .C2(n111), .A(n112), .ZN(n90) );
  OAI222_X2 U9 ( .A1(n114), .A2(n115), .B1(n85), .B2(n116), .C1(n117), .C2(
        n118), .ZN(n113) );
  AOI221_X2 U10 ( .B1(n45), .B2(n36), .C1(n43), .C2(n52), .A(n119), .ZN(n110)
         );
  NOR4_X2 U11 ( .A1(indexY[3]), .A2(indexX[1]), .A3(n65), .A4(n120), .ZN(n119)
         );
  AOI221_X2 U13 ( .B1(n31), .B2(n65), .C1(n72), .C2(n11), .A(n121), .ZN(n88)
         );
  ...
  NOR3_X2 U396 ( .A1(n99), .A2(indexY[1]), .A3(n100), .ZN(n92) );
  NAND3_X2 U399 ( .A1(n100), .A2(n134), .A3(n349), .ZN(n346) );
  NAND3_X2 U405 ( .A1(indexX[0]), .A2(indexX[2]), .A3(n63), .ZN(n349) );
  NAND3_X2 U409 ( .A1(n42), .A2(n79), .A3(indexX[0]), .ZN(n134) );
  NAND3_X2 U411 ( .A1(indexY[2]), .A2(n58), .A3(n80), .ZN(n145) );
  NAND3_X2 U412 ( .A1(n427), .A2(n293), .A3(n428), .ZN(n419) );
  OAI21_X2 U423 ( .B1(n393), .B2(n15), .A(n62), .ZN(n427) );
  NOR2_X2 U426 ( .A1(indexX[3]), .A2(n105), .ZN(n350) );
  NOR2_X2 U427 ( .A1(indexX[2]), .A2(n65), .ZN(n177) );
  NAND3_X2 U429 ( .A1(n315), .A2(n316), .A3(n317), .ZN(n310) );
  NAND3_X2 U431 ( .A1(indexY[1]), .A2(indexX[3]), .A3(n40), .ZN(n316) );
  OAI21_X2 U432 ( .B1(n83), .B2(n72), .A(n2), .ZN(n315) );
  INV_X4 U443 ( .A(indexX[0]), .ZN(n58) );
  INV_X4 U444 ( .A(indexX[1]), .ZN(n49) );
  INV_X4 U445 ( .A(indexY[2]), .ZN(n79) );
endmodule


and this one is lookup synthase file when synthesis alone(as an independent module)
Code Verilog - [expand]
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module lookup ( indexX, indexY, intermediate );
  input [3:0] indexX;
  input [3:0] indexY;
  output [7:0] intermediate;
  wire   N165, N269, N377, N471, N564, N641, N714, N778, n442, n443, n444,
         n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455,
         n456, n457, n458, n459, n460, n461, n462, n463, n464, n465, n466,
         n467, n468, n469, n470, n471, n472, n473, n474, n475, n476, n477,
         ...
  assign intermediate[7] = N165;
  assign intermediate[6] = N269;
  assign intermediate[5] = N377;
  assign intermediate[4] = N471;
  assign intermediate[3] = N564;
  assign intermediate[2] = N641;
  assign intermediate[1] = N714;
  assign intermediate[0] = N778;
 
  NAND4_X1 U450 ( .A1(n442), .A2(n443), .A3(n444), .A4(n445), .ZN(N778) );
  NOR4_X1 U451 ( .A1(n446), .A2(n447), .A3(n448), .A4(n449), .ZN(n445) );
  OAI33_X1 U452 ( .A1(n450), .A2(n451), .A3(n452), .B1(n453), .B2(n454), .B3(
        n455), .ZN(n449) );
  NOR2_X1 U453 ( .A1(n456), .A2(n457), .ZN(n454) );
  AOI21_X1 U454 ( .B1(n458), .B2(n459), .A(n460), .ZN(n448) );
  OAI21_X1 U455 ( .B1(n461), .B2(n462), .A(n463), .ZN(n447) );
  OAI21_X1 U456 ( .B1(n464), .B2(n465), .A(n466), .ZN(n463) );
  INV_X1 U457 ( .A(n467), .ZN(n464) );
  OAI221_X1 U458 ( .B1(n468), .B2(n469), .C1(n470), .C2(n471), .A(n472), .ZN(
        n446) );
  AOI222_X1 U459 ( .A1(n473), .A2(n474), .B1(n475), .B2(n476), .C1(n477), .C2(
        n478), .ZN(n472) );
  NOR3_X1 U460 ( .A1(n479), .A2(n480), .A3(n465), .ZN(n470) );
  NOR3_X1 U461 ( .A1(n481), .A2(indexX[1]), .A3(n482), .ZN(n479) );
  INV_X1 U462 ( .A(n483), .ZN(n468) );
  AOI211_X1 U463 ( .C1(n480), .C2(n484), .A(n485), .B(n486), .ZN(n444) );
  MUX2_X1 U464 ( .A(n487), .B(n488), .S(n489), .Z(n486) );
  ...
  INV_X1 U904 ( .A(n481), .ZN(n476) );
  NAND2_X1 U905 ( .A1(n637), .A2(n777), .ZN(n481) );
  INV_X1 U906 ( .A(indexX[2]), .ZN(n777) );
  INV_X1 U907 ( .A(indexX[3]), .ZN(n637) );
  INV_X1 U908 ( .A(n860), .ZN(n582) );
  NAND2_X1 U909 ( .A1(indexX[0]), .A2(n778), .ZN(n860) );
  INV_X1 U910 ( .A(indexX[1]), .ZN(n778) );
endmodule


i thought these two files must be same ??? i was going to do what you said in previous post but i notice those verilog coded that start with 'assign' are change in context of nand form ???? the second one is the correct that when converted to first one along with other module codes get incorrect
 

You should try to be concise and state exactly which code is for what. Right now I'm not sure if the top file works or the bottom one works or none of them work. I'm also not sure if the top was from bottom up synthesis or from just synthesis of the file alone. Or maybe you've done bottom up for the 1st code and a standalone (lookup as the top-level) synthesis for the 2nd code?

Which one produces X's on intermediate, both version or only the 2nd code? Right now I'm not sure which code you are running in your simulation on.

Originally you posted this as your top level lookup file:
Code Verilog - [expand]
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module lookup(indexX, indexY , clk  ,out_port);
input [3:0] indexX;
input [3:0] indexY;
input  clk;
output out_port;
 
wire [7:0] temp;
 
mem insMem(.IndexX(indexX),.indexY(indexY),.intemediate(temp));
regOut insRegOut(.inp(temp),.clk(clk),.out_port(out_port));
 
endmodule

The ports are inconsistent with what you just posted above for lookup, which instead matches the ports on the module mem!? So is this just another typo (you need to be more careful of those) because I'm confused as to which module you are even synthesizing.

I'm just about ready to give up, normally given the right information from the start this should have been solved before 34 posts on the subject, and right now I don't see it getting solved in 34 more posts.
 

really sorry, you are right i should have explained more precisely
my design structure is like this:

Sbox is top module and contains two other modules 'lookup' and 'regout'
i first synthesis lookup and post simulate it and everything is right and this is a piece of synthesis file by DC
Code Verilog - [expand]
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module lookup ( indexX, indexY, intermediate );
  input [3:0] indexX;
  input [3:0] indexY;
  output [7:0] intermediate;
  wire   N165, N269, N377, N471, N564, N641, N714, N778, n442, n443, n444,
         n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455,
         n456, n457, n458, n459, n460, n461, n462, n463, n464, n465, n466,
         n467, n468, n469, n470, n471, n472, n473, n474, n475, n476, n477,
         n478, n479, n480, n481, n482, n483, n484, n485, n486, n487, n488,
         ...
 
  assign intermediate[7] = N165;
  assign intermediate[6] = N269;
  assign intermediate[5] = N377;
  assign intermediate[4] = N471;
  assign intermediate[3] = N564;
  assign intermediate[2] = N641;
  assign intermediate[1] = N714;
  assign intermediate[0] = N778;
 
  NAND4_X1 U450 ( .A1(n442), .A2(n443), .A3(n444), .A4(n445), .ZN(N778) );
  NOR4_X1 U451 ( .A1(n446), .A2(n447), .A3(n448), .A4(n449), .ZN(n445) );
  OAI33_X1 U452 ( .A1(n450), .A2(n451), .A3(n452), .B1(n453), .B2(n454), .B3(
        n455), .ZN(n449) );
  NOR2_X1 U453 ( .A1(n456), .A2(n457), .ZN(n454) );
  AOI21_X1 U454 ( .B1(n458), .B2(n459), .A(n460), .ZN(n448) );
  OAI21_X1 U455 ( .B1(n461), .B2(n462), .A(n463), .ZN(n447) );
  OAI21_X1 U456 ( .B1(n464), .B2(n465), .A(n466), .ZN(n463) );
  INV_X1 U457 ( .A(n467), .ZN(n464) );
  OAI221_X1 U458 ( .B1(n468), .B2(n469), .C1(n470), .C2(n471), .A(n472), .ZN(
        n446) );
  AOI222_X1 U459 ( .A1(n473), .A2(n474), .B1(n475), .B2(n476), .C1(n477), .C2(
        n478), .ZN(n472) );
  NOR3_X1 U460 ( .A1(n479), .A2(n480), .A3(n465), .ZN(n470) );
  NOR3_X1 U461 ( .A1(n481), .A2(indexX[1]), .A3(n482), .ZN(n479) );
  INV_X1 U462 ( .A(n483), .ZN(n468) );
 ...
 
  INV_X1 U898 ( .A(n701), .ZN(n456) );
  NAND2_X1 U899 ( .A1(n655), .A2(n580), .ZN(n701) );
  INV_X1 U900 ( .A(indexY[0]), .ZN(n580) );
  INV_X1 U901 ( .A(indexY[2]), .ZN(n655) );
  INV_X1 U902 ( .A(n693), .ZN(n699) );
  NAND2_X1 U903 ( .A1(n582), .A2(n476), .ZN(n693) );
  INV_X1 U904 ( .A(n481), .ZN(n476) );
  NAND2_X1 U905 ( .A1(n637), .A2(n777), .ZN(n481) );
  INV_X1 U906 ( .A(indexX[2]), .ZN(n777) );
  INV_X1 U907 ( .A(indexX[3]), .ZN(n637) );
  INV_X1 U908 ( .A(n860), .ZN(n582) );
  NAND2_X1 U909 ( .A1(indexX[0]), .A2(n778), .ZN(n860) );
  INV_X1 U910 ( .A(indexX[1]), .ZN(n778) );
endmodule


this time i bottom-up module Sbox that contains both lookup and regOut moduls that post synthesis simulation is not correct and all outputs are x (as i have posted in previous snapshopts ) and this is a piece of synthesis code related to lookup and regOut and Sbox in this scenario(created by DC):
Code Verilog - [expand]
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module lookup ( indexX, indexY, intermediate );
  input [3:0] indexX;
  input [3:0] indexY;
  output [7:0] intermediate;
  wire   N165, N269, N377, N471, N564, N641, N714, N778, n1, n2, n3, n4, n5,
         n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20,
         n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34,
         n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48,
         ...
         n381, n382, n383, n384, n385, n386, n387, n388, n389, n390, n391,
         n392, n393, n394, n395, n396, n397, n398, n399, n400, n401, n402,
         n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, n413,
         n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424,
         n425, n426, n427, n428, n429, n84, n86, n430, n431, n432;
 
  assign intermediate[7] = N165;
  assign intermediate[6] = N269;
  assign intermediate[5] = N377;
  assign intermediate[4] = N471;
  assign intermediate[3] = N564;
  assign intermediate[2] = N641;
  assign intermediate[1] = N714;
  assign intermediate[0] = N778;
 
  NAND4_X2 U1 ( .A1(n87), .A2(n88), .A3(n89), .A4(n90), .ZN(N778) );
  NOR4_X2 U2 ( .A1(n91), .A2(n92), .A3(n93), .A4(n28), .ZN(n90) );
  AOI221_X2 U7 ( .B1(n56), .B2(n108), .C1(n65), .C2(n109), .A(n110), .ZN(n89)
         );
  OAI222_X2 U8 ( .A1(n111), .A2(n112), .B1(n113), .B2(n114), .C1(n115), .C2(
        n116), .ZN(n110) );
  AOI22_X2 U9 ( .A1(n117), .A2(n42), .B1(n44), .B2(indexY[3]), .ZN(n113) );
  OAI221_X2 U11 ( .B1(n118), .B2(n119), .C1(n120), .C2(n121), .A(n122), .ZN(
        n109) );
  AOI221_X2 U12 ( .B1(n81), .B2(n123), .C1(n71), .C2(n124), .A(n125), .ZN(n88)
         );
  ...
  NAND3_X2 U583 ( .A1(indexX[1]), .A2(n50), .A3(n74), .ZN(n133) );
  NAND3_X2 U584 ( .A1(indexX[0]), .A2(n78), .A3(n82), .ZN(n417) );
  NAND3_X2 U585 ( .A1(indexX[2]), .A2(n55), .A3(n60), .ZN(n357) );
  NOR2_X2 U586 ( .A1(indexY[3]), .A2(n10), .ZN(n117) );
  NOR2_X2 U587 ( .A1(indexX[0]), .A2(n78), .ZN(n348) );
  INV_X4 U588 ( .A(indexX[0]), .ZN(n55) );
  INV_X4 U589 ( .A(indexX[1]), .ZN(n46) );
  INV_X4 U590 ( .A(indexY[2]), .ZN(n78) );
  INV_X4 U591 ( .A(indexX[3]), .ZN(n35) );
endmodule
 
 
module regOut ( inp, outp, clk, reset );
  input [7:0] inp;
  output [7:0] outp;
  input clk, reset;
  wire   n1;
 
  SDFF_X2 \outp_reg[7]  ( .D(1'b0), .SI(n1), .SE(inp[7]), .CK(clk), .Q(outp[7]) );
  SDFF_X2 \outp_reg[6]  ( .D(1'b0), .SI(n1), .SE(inp[6]), .CK(clk), .Q(outp[6]) );
  SDFF_X2 \outp_reg[5]  ( .D(1'b0), .SI(n1), .SE(inp[5]), .CK(clk), .Q(outp[5]) );
  SDFF_X2 \outp_reg[4]  ( .D(1'b0), .SI(n1), .SE(inp[4]), .CK(clk), .Q(outp[4]) );
  SDFF_X2 \outp_reg[3]  ( .D(1'b0), .SI(n1), .SE(inp[3]), .CK(clk), .Q(outp[3]) );
  SDFF_X2 \outp_reg[2]  ( .D(1'b0), .SI(n1), .SE(inp[2]), .CK(clk), .Q(outp[2]) );
  SDFF_X2 \outp_reg[1]  ( .D(1'b0), .SI(n1), .SE(inp[1]), .CK(clk), .Q(outp[1]) );
  SDFF_X2 \outp_reg[0]  ( .D(1'b0), .SI(n1), .SE(inp[0]), .CK(clk), .Q(outp[0]) );
  INV_X4 U1 ( .A(reset), .ZN(n1) );
endmodule
 
 
module Sbox_1 ( indexX, indexY, clk, reset, out_port );
  input [3:0] indexX;
  input [3:0] indexY;
  output [7:0] out_port;
  input clk, reset;
 
  wire   [7:0] temp;
 
  lookup ins_lookup ( .indexX(indexX), .indexY(indexY), .intermediate(temp) );
  regOut ins_regout ( .inp(temp), .outp(out_port), .clk(clk), .reset(reset) );
endmodule


1) in my previous post i said these two output are not same, that after change some script they now get more similar
2) you said change 'assign intermediate =N??' to 'assign intermediate='1'b1' , i already did and my output is no longer X
3) i select lookup part of synthesis code in second scenario and simulate it alone in order to find out whether it is correct (in comparison with lookup module that had been simulated in first scenario ) and i saw, yep it is correct
4) based on 3 i conclude that when in bottom-up synthesis something design compiler does something wrong because even in second senario when i select each module and simulate it standalone i see everything is right but when they reside beside each other(in top module so-called Sbox) they didn't work
5) i track down X outputs and saw that output of lookup is x that lead to input of regOut goes x then goes output of Sbox goes x
i hope this time i could have convey it appropriately
 

hi Dear ads-ee
my problem solved , actually the problem was not about lookup module(combinational part) , i dont know why regOut (sequential logic) work incorrectly after syntheses , i try to change of used flip flops form SDFF to DFF and also add sttribute 'set_dont_touch' for signal reset of regOut and everything work correctly . acutally i still don't why should changing flip flop type helped

but i have another problem, when i give Design Comiler outputs including (netlist, spef file, sdc file, ddc file and library file) to Prime Time (in order to analyses power)i get these errors

read_parasitics ./out/Sbox.spef
Information: Derived library resistance unit is 1.000000 Kohm (Time unit is 1 ns, and Capacitance unit is 1.000000 pF). (DES-028)
Error: Cannot find port/pin 'ins_lookup/U534/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U568/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U576/A2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U591/A' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U337/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U297/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U279/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U272/B1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U268/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U104/C1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U535/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U552/A2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U554/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U582/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U337/A2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U313/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U278/B1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U73/B2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U381/A' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U537/A2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U538/A2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U552/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U558/C1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U572/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U575/B1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U580/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U586/A' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U322/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U311/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U301/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U300/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U297/A2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U290/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U282/A2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U220/B2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U217/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U191/B1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U146/C1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U545/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U556/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U566/B1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U569/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U576/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U581/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U584/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U585/A' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U314/A2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U283/A2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U273/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U536/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U549/C1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U550/A2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U570/A2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U579/A' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U583/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U322/A2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U319/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U283/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U282/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U276/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U265/A1' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U224/A2' in design 'Sbox_1' (DES-002)
Error: Cannot find port/pin 'ins_lookup/U144/C1' in design 'Sbox_1' (DES-002)
...
Error: Could not resolve net 'ins_lookup/n427'. (PARA-075)
Error: Could not resolve net 'ins_lookup/n428'. (PARA-075)
Error: Could not resolve net 'ins_lookup/n429'. (PARA-075)
Error: Could not resolve net 'ins_lookup/n84'. (PARA-075)
Error: Could not resolve net 'ins_lookup/n86'. (PARA-075)
Error: Could not resolve net 'ins_lookup/n430'. (PARA-075)
Error: Could not resolve net 'ins_lookup/n431'. (PARA-075)
Error: Could not resolve net 'ins_lookup/n432'. (PARA-075)
Error: Could not resolve net 'ins_regout/N3'. (PARA-075)
Error: Could not resolve net 'ins_regout/N4'. (PARA-075)
Error: Could not resolve net 'ins_regout/N5'. (PARA-075)
Error: Could not resolve net 'ins_regout/N6'. (PARA-075)
Error: Could not resolve net 'ins_regout/N7'. (PARA-075)
Error: Could not resolve net 'ins_regout/N8'. (PARA-075)
Error: Could not resolve net 'ins_regout/N9'. (PARA-075)
Error: Could not resolve net 'ins_regout/N10'. (PARA-075)
Error: Could not resolve net 'ins_regout/n9'. (PARA-075)

****************************************
Report : read_parasitics /root/Desktop/Dpa_V2/out/Sbox.spef
Design : Sbox_1
Version: D-2009.12-SP3
Date : Thu Jul 9 07:47:29 2015
****************************************

602 error(s)
Format is SPEF
Annotated nets : 26
Annotated capacitances : 0
Annotated resistances : 0
Reduced coupling capacitances : 0
Annotated PI models : 10
Annotated Elmore delays : 0

any idea , what is wrong with spef file ?
 

I was looking at your previous post earlier today and was going to ask you why a D-FF was implemented as:
Code: 
SDFF_X2 \outp_reg[7]  ( .D(1'b0), .SI(n1), .SE(inp[7]), .CK(clk), .Q(outp[7]) );
That really isn't a D-FF, hooked up the way it is with the D input grounded. I'm assuming the SI and SE are scan input and scan enable. Why DC would implement your code like this is a complete mystery to me.

I was planning on having your drive the assign intermediate with 1'b0 and not 1'b1 as you seem to had done. What I was trying to get you to do was to systematically determine where the problem was by breaking the path that had the X into separate sides so you could check the N?? value and the output to see where the X was really at. Still not entirely sure why the scan flop would generate an X.

If D == 0, SI = ~reset (your original code did not have a reset), and SE == inp, would seem to mean that when you get a 1 on the SE input you would get the inverted reset (active high?) on the output which would be a 1? And if SE has a 0 on the input then the D ends up at the output so it's 0. Logically it should work, but I don't know what is the real truth table of that SDFF.



This other issue, you'll have to determine if there is some hierarchical name problem. See if you can find one of the U??/? in the netlist. Also make sure you are applying it to the right level of hierarchy. Like I said I haven't worked with Prime time in decades, so I can only give general advice on how to go about debugging such a problem.
 

my second problem solved, i just changed set link_library ./db/NangateOpenCellLibrary_45nm.db to set link_library [list * ./db/NangateOpenCellLibrary_45nm.db] ?? actually i don't know why it solved but it worked
 

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