Design compiler syntax error near or at token library

hi

when i execute this script i get this error from DC can anyone help me?

thanks in advance

Error: ./third.vhd:5: Syntax error at or near token 'library'. (VER-294)

this is my vhdl code




library IEEE;
use IEEE.STD_LOGIC_1164.ALL;







entity third is
Port ( data_in : in STD_LOGIC_VECTOR (31 downto 0);
output : out STD_LOGIC_VECTOR (32 downto 0));
end third;

architecture Behavioral of third is

type t_array is array (0 to 32) of std_logic_vector(32 downto 0);

type d_array is array (0 to 32) of std_logic_vector(31 downto 0);


CONSTANT data_array : d_array :=(x"00000000",x"0000ffff",x"00000300",x"00000600",
x"01fd0000",x"0180c000",x"0000003b",x"01fee000",x"01fd4000",x"00000001",x"00010000",
x"00000002",x"00000700",x"000002a1",x"025d8cc0",x"0000001f",x"ffffffff",x"13131313",
x"12121212",x"ffff0000",x"14141414",x"00000004",x"15151515",x"1f1f1f1f",x"18181818",x"13131212",
x"02000000",x"14131313",x"13131314",x"00000200",x"14141313",x"13131312",x"13121212");

CONSTANT tag_array: t_array:=("000000000000000000000000000000000",
"000000000000000000000000000000001",
"000000000000000000000000000000010",
"000000000000000000000000000000100",
"000000000000000000000000000001000",
"000000000000000000000000000010000",
"000000000000000000000000000100000",
"000000000000000000000000001000000",
"000000000000000000000000010000000",
"000000000000000000000000100000000",
"000000000000000000000001000000000",
"000000000000000000000010000000000",
"000000000000000000000100000000000",
"000000000000000000001000000000000",
"000000000000000000010000000000000",
"000000000000000000100000000000000",
"000000000000000001000000000000000",
"000000000000000010000000000000000",
"000000000000000100000000000000000",
"000000000000001000000000000000000",
"000000000000010000000000000000000",
"000000000000100000000000000000000",
"000000000001000000000000000000000",
"000000000010000000000000000000000",
"000000000100000000000000000000000",
"000000001000000000000000000000000",
"000000010000000000000000000000000",
"000000100000000000000000000000000",
"000001000000000000000000000000000",
"000010000000000000000000000000000",
"000100000000000000000000000000000",
"001000000000000000000000000000000",
"010000000000000000000000000000000");


begin



process(data_in )
variable temp: std_logic_vector(32 downto 0);
begin
temp :="111111111111111111111111111111111";
for i in 0 to 32 LOOP

if ( data_in=data_array(i)) THEN


output <= tag_array (i); else


temp(31 downto 0):=data_in;

output<=temp;


end if;
end loop;
end process;




end Behavioral;


and this is my script

set my_files third.vhd
set my_toplevel third
set my_clock_pin CLK
set my_clk_freq_MHz 100
set my_input_delay_ns 0
set my_output_delay_ns 0
set link_library ./osu025_stdcells.db
set target_library ./osu025_stdcells.db
define_design_lib WORK -path ./WORK
set compile_ultra true
analyze -f verilog $my_files
elaborate $my_toplevel
current_design $my_toplevel
link
uniquify
set my_period [expr 1000 / $my_clk_freq_MHz]
set find_clock [ find port [list $my_clock_pin] ]
if { $find_clock !=

• } {
  set clk_name $my_clock_pin
  create_clock -period $my_period $clk_name
  } else {
  set clk_name vclk
  create_clock -period $my_period -name $clk_name
  }
  set_driving_cell -lib_cell INVX8 [all_inputs]
  set_input_delay $my_input_delay_ns [all_inputs]
  set_output_delay $my_output_delay_ns [all_outputs]
  compile -ungroup_all -map_effort medium
  compile -incremental_mapping -map_effort medium
  check_design
  report_timing
  report_timing -delay min
  report_timing -delay max
  report_timing -delay max > max_tim.rpt
  report_timing -delay min > min_tim.rpt
  
  write -f ddc -o ./Reports/myddc.ddc
  write -f verilog -o ./Reports/netlist_verilog.v
  write -f vhdl -o ./Reports/netlist_vhdl.vhdl
  write_sdf ./Reports/Stndrd_Dly_Frmt.sdf
  write_parasitics -o ./Reports/C_R_delays.spef
  write_sdc ./Reports/sdc.sdc

Hi ranjbar_7,
When i copied the code and compiled it with ModelSim i found that there is some extra space in the following numbers at the constant declaration place,

x" 01fd4000"
x" 0000001f"
x" 15151515"
x" 14141313"

when i removed the space and compiled it there was no error...

x"01fd4000"
x"0000001f"
x"15151515"
x"14141313"

Thank you very much

- - - Updated - - -

Thank you very much