master_picengineer
Banned
Hi Everybody,
I need to design a synchronizer operating at least at 20 Ghz. I designed a DFF with Design Compiler and using the newest Standards cell library. For this library the maximum frequency constrain for a simple DFF is around 1.3 Ghz. I understood that I can't go further in frequency and that the synchronizer will operate at inferior rate.
1 / Please can some one tell me how to design Digital High speed (Multi-Ghz) devices in VHDL. Is that possible ?
if no
2/ How may I build my synchronizer ? Should I move to design it at the transistor level with the conventional analog design tools ?
Please dont hesitate to poste replies.
Thanks a lot,
Cheers,
Master_PicEngineer
I need to design a synchronizer operating at least at 20 Ghz. I designed a DFF with Design Compiler and using the newest Standards cell library. For this library the maximum frequency constrain for a simple DFF is around 1.3 Ghz. I understood that I can't go further in frequency and that the synchronizer will operate at inferior rate.
1 / Please can some one tell me how to design Digital High speed (Multi-Ghz) devices in VHDL. Is that possible ?
if no
2/ How may I build my synchronizer ? Should I move to design it at the transistor level with the conventional analog design tools ?
Please dont hesitate to poste replies.
Thanks a lot,
Cheers,
Master_PicEngineer