design compiler & physical compiler

Status
Not open for further replies.

renoz

Member level 3
Joined
Aug 27, 2011
Messages
54
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,587
hi

am beginner
please give the basic detail about design compiler & physical,memory,RTL compiler

whats use of these:?:


thanks & regard
 

Design compiler is a RTL synthesis tool by synopsys , which is used to generate Netlist n Gate level synthesis.
 

Of many EDA companies Design compiler and RTLCompiler are RTL synthesis products from Synopsys and Cadence - RTL to technology gates mapping and optimization
Physical Compiler or ICC compiler is the PnR tool of Synopsys; Encounter Digital Implementation from Cadence - used for placement, clock tree routing and physical optimization.
 
Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…