alokkmr18
Junior Member level 1
hello every one ...
Can anybody tell me how we simulate netlist(gate level) file after doing rtl-gate level synthesis.
I m using Design comlier(synopsys) for synthesis of standard cells in VHDL. After doing successful synthesis it generates gate level netlist which i have to simulate to verify the functionality of standard cells. Simulator is ncSim.
When i trying to simulate in ncsim it shows error that
ncelab: *E,DLOALB:: Design library 'ieee' not defined while reading package ieee.std_logic_1164 (AST)
and i can't get that errors.
Looking for positive response from anyone.
Can anybody tell me how we simulate netlist(gate level) file after doing rtl-gate level synthesis.
I m using Design comlier(synopsys) for synthesis of standard cells in VHDL. After doing successful synthesis it generates gate level netlist which i have to simulate to verify the functionality of standard cells. Simulator is ncSim.
When i trying to simulate in ncsim it shows error that
ncelab: *E,DLOALB:: Design library 'ieee' not defined while reading package ieee.std_logic_1164 (AST)
and i can't get that errors.
Looking for positive response from anyone.