Design approach for a interface mux

[er.akhilkumar]

Hi all,

I have a situation in which a FIFO can be written by two interfaces: one is the direct FIFO interface (for fast data transfer), another is an interface coming from the Register Map. I need to develop a mux to select between these two interfaces on the basis of a control bit. Both interfaces have different clocks. So, I need to implement CDC as well. Can you please suggest a good approach to implement this?

Thanks.

 

[KlausST]

Hi,

I´d start with what a design should start: Defining the requirements, like timing, signals ... then drawing a sketch....

Requirments alo are:
* who is the master
* what happens when both interfaces want to write
* what the protocol needs to be, so the receiver can correctly define the data
* what is the master clock
* and so on

Klaus

 

[barry]

one of the great features of a FIFO is handling multiple clock domains; you’re throwing that away. Maybe you could use one FIFO for each clock domain and multiplex the FIFO outputs. Not sure if that would work for your particular situation

 

[FvM]

Maybe you could use one FIFO for each clock domain and multiplex the FIFO outputs.

Sounds promising, at least all timing requirements can be most likely achieved this way.

However, you'll start with a specification of all related signals, we don't even know if the main FIFO path is single or dual clock?