Design and Layout driven Strength Which is better ?

[AdvaRes]

Hi members,

Let's take an AND gate for exemple. Suppose we'll design a AND gate with a drive strength=4.
The figure 1 shows the AND gate transistor sizing for a drive strength=1.

Figure 2 and Figure 3 are two possibles implementation of an AND gate with a drive strenth=4.

My question is: Which is better the AND of figure 2 or in figure 3 ?

Thanks in advance.

 

[ravirajdv]

Hi AdvaRes,
In Fig 2, I guess only the o/p stage has the specified W and L's.
Fig 2 and Fig 3 are the same except the arch in fig 3 has fingered mos devices, this would reduce the intermediate parasitic caps due to drain and source. Also we can optimize the area, if we break the o/p devices in fingers, so that the entire AND is fit in a rectagle of area.

Regards,
RDV

 

[AdvaRes]

Hi AdvaRes,
In Fig 2, I guess only the o/p stage has the specified W and L's.

Hi ravirajdv,
Actutually, the specified W and L are for all the transistors not only for the O/P stage.
Also if only the o/p stage has the specified W and L's the drive strength is 4. If you like we can discuss the performance of these differents schematics in terms of speed, area power consumption.

Thanks.

 

[ravirajdv]

Hi AdvaRes,
It would be better if you have only the o/p stage of 4X strength and the nand structure can be of either 1X or 2X depends on the need (like the Rise time and fall time at the input of the 2nd stage), but surely we can drop the sizes in the input part (nand stage).
Advantages:
1> area is reduced
2> since the input size is less, the load on the previous stage is reduced, indirectly reducing the power.
Also, the power consumption depends more on the load and the frequency of operation of the nand, then the device sizes.
Is this nand you are doing is for some PLL? (Sorry, out of context question)
Regards,
RDV

 

[AdvaRes]

Hi AdvaRes,
It would be better if you have only the o/p stage of 4X strength and the nand structure can be of either 1X or 2X depends on the need (like the Rise time and fall time at the input of the 2nd stage), but surely we can drop the sizes in the input part (nand stage).
Advantages:
1> area is reduced
2> since the input size is less, the load on the previous stage is reduced, indirectly reducing the power.
Also, the power consumption depends more on the load and the frequency of operation of the nand, then the device sizes.
Is this nand you are doing is for some PLL? (Sorry, out of context question)
Regards,
RDV

That's Clear
Thanks man !
Yeah, It's for a PFD of a PLL.

 

[ravirajdv]

Hi,
I am also doing the same thing, hope we will discuss more about these and the PLL stuff as we go ahead.
A suggestion, try to make a the the A and B inputs symmtrical so that both the REFCLK and the FBCLK see the same delay from A to Y.
Thanks and Cheers,
RDV

 

[AdvaRes]

Hi,
I am also doing the same thing, hope we will discuss more about these and the PLL stuff as we go ahead.
A suggestion, try to make a the the A and B inputs symmtrical so that both the REFCLK and the FBCLK see the same delay from A to Y.
Thanks and Cheers,
RDV

You are welcome man !
Thanks for the advise.
But we forgot to discuss the layout drawing time required. Actually it is much more easy to draw the layout of the Figure 2 using the Layout of the figure 1. Figure 3 Layout requires more time to be done.

 

[sandeep_torgal]

You are welcome man !
Thanks for the advise.
But we forgot to discuss the layout drawing time required. Actually it is much more easy to draw the layout of the Figure 2 using the Layout of the figure 1. Figure 3 Layout requires more time to be done.

If you fix the height of the cell, then fig 3 and fig 2 might take almost the same time...