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Hi all;
i want to design a system with 2 processor wich one of those is a protection of another.
please help me for architecture of DATA and ADDRESS bus.
What do you mean about "protection"? A fault tolerant system, perchance?
In any case, the data and address bus architecture will pretty much be determined by the CPUs. Unless, of course, you also have to design the CPU's, in which case this sounds like a homework to me....
The processor will be used in the controller board of a SDH STM-4 system.We want to design a redundant controller board which is hot stand-by. We have not complete information about such designs. we would be grateful if you provide us with some documents or whatever which could be useful in this regard.
Meanwhile, we have a problem with multi-slot (board) design, specifically about how to route address bus and data bus, and what architecture to use. (for example some designers use of master-slave configuration in their design (a controller in the main card and a slave controller in the other card)). We would be grateful if you give us some information, although little, about this, too.
If you look for a cook-book approach, that may be difficult to find for your case.
One of the seminal book in Computer Architecture is: "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson. It should have most of what you need, and you should read and really understand the applicable portions of it.
I don't fully understand the reasoning behind your hot spare. As long as the operating conditions are in the proper range (mostly temp and voltages) CPUs don't usually fail. But let assume it does fail, but then how do you detect the failure with one spare? You can probably detect many catastrophic failures, but detecting subtle bugs (like the floating point bug on the early Pentiums) will be next to impossible.
Where utmost reliability is required, one can use 3 CPUs, all doing the same computation parallel, and use voting if 2 outputs disagree. And if CPU generates incorrect result several times over a given period, one can conclude that it's defective and deactivate it. With only 2 CPUs, one can conclude that one of them had failed (or produced an incorrect result) but figuring out which one is bad is a bit tricky, especially if the failure is intermittent.
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