Design a comparator.

[quocviet19501]

Hi all, thank you for reading my post. I need to design a comparator, because of FIFO problem I have to use the almost_rempty signal to read the data from 1 block (gen block) and signal ren to read data from FIFO block. In the picture below, you can see that when reading the expected_data from gen block it misses 2 final data since the almost_rempty is faster than rempty (assert when FIFO is empty) signal 2 clk cycles. Can anyone suggest a solution?

 

[KlausST]

Hi,

I guess you missed to give a lot of informations.

The headline says "design a comparator".
At first I thought of an analog comparator, but soon recognized it rather should be a digital one.
A comparator usually has to inputs and one output.
You completely missed to define each input(bit width? signed?...) and the output (=, <, >, <=, >=)
What's exactly the problem? Why can't you desgn it on your own? What help exactly do you need?

Then "text" vs "diagram"
* FIFO: I don' see a FIFO at all
* "to read the data from 1 block (gen block)" : I don't see "data", "1 block", "gen block"...

In the picture below, you can see that when reading the expected_data from gen block it misses 2 final data

No. I see that rdata is the same as expected_data. If it's like expected... where is the problem?

Can anyone suggest a solution?

As description? As code - what language? As schematic/logic?

Usually the forum is not meant to provide ready to use solutions. The forum is meant to give assistance in teaching you .. or to correct mistakes in your work. But we don't see what you have done/tried so far.

So please give a detailed description of the problem, including code/schematic/flow chart/ drafts .. where we can see all the signals you are talking about .... and the overall function.

Also tell us where exactly you need help, what you understand so far and is not clear.

Klaus

 

[kaz1]

Hi all, thank you for reading my post. I need to design a comparator, because of FIFO problem I have to use the almost_rempty signal to read the data from 1 block (gen block) and signal ren to read data from FIFO block. In the picture below, you can see that when reading the expected_data from gen block it misses 2 final data since the almost_rempty is faster than rempty (assert when FIFO is empty) signal 2 clk cycles. Can anyone suggest a solution?
View attachment 184709

why not use ren as your signal to compare data. If data is late by one clock then delay ren by one clock to ren_d.

 

[quocviet19501]

Hi,

I guess you missed to give a lot of informations.

The headline says "design a comparator".
At first I thought of an analog comparator, but soon recognized it rather should be a digital one.
A comparator usually has to inputs and one output.
You completely missed to define each input(bit width? signed?...) and the output (=, <, >, <=, >=)
What's exactly the problem? Why can't you desgn it on your own? What help exactly do you need?

Then "text" vs "diagram"
* FIFO: I don' see a FIFO at all
* "to read the data from 1 block (gen block)" : I don't see "data", "1 block", "gen block"...

No. I see that rdata is the same as expected_data. If it's like expected... where is the problem?


As description? As code - what language? As schematic/logic?

Usually the forum is not meant to provide ready to use solutions. The forum is meant to give assistance in teaching you .. or to correct mistakes in your work. But we don't see what you have done/tried so far.

So please give a detailed description of the problem, including code/schematic/flow chart/ drafts .. where we can see all the signals you are talking about .... and the overall function.

Yes, it is a digital comparator.

its inputs: clk, rst_n, cmp_en(enable the comparator), rdata (asyn FIFO data), rempty, almost_empty (2clk cycles faster than empty), expected_data (from block name pattern generator).

 

[quocviet19501]

what I need is simply how to extend the almost_empty signal to 2 more clk cycles so it can capture 2 more data for comparing process.

 

[kaz1]

If you are not using ren_d then just extend almost empty two clocks as follows:
clocked process:
almost_empty_1d <= almost_empty;
almost_empty_2d < = almost_empty_1d;

combinatorial:
almost_enable_ored <= almost_empty or almost_empty_1d or almost_empty_2d