Design a cmos LNA with the input nmos working in sub-threshold region

[AllenD]

Hi Team,
I have a favor to ask.
Background:
I am trying to design a wide-band cmos LNA with certain topology. I started with my baseline design. Then I discovered that the performance of the LNA can be drastically improved if I kept the drain current same (Id=1.8 mA in my case) while increase the W/L of the input mosfet (the nmos whose gate is the input node). However, this forced the input nmos working in sub-threshold region(Vgs < Vth) while in my baseline design, the input nmos is working in saturation.

Questions:
1. Is sub-threshold region a reliable region to operate if I want to tapeout my circuit?
2. Comparing my baseline design to the new design, the major trade-off is that I gain the LNA performance and lose the input nmos operating region (from saturation to sub-threshold.) Can you please comment on this trade-off?

Thanks
Allen

 

[frankrose]

1. yes, but without schematic hard to say it can cause a problem. if you generate operating current for the amplifier device with a current mirror, sub-threshold can cause problem for example.
2. deep-subtrheshold is not effective, because gm of the LNA won't increase with the width, however input capacitance will grow. Edge of sub-threshold/saturation region is better, because the gm is quite high, but input capacitance is not too high, just check the CV curve. trade-off occurs when you use the device as a DC current mirror, otherwise I am not sure it is a trade-off.

 

[AllenD]

Hi Frankrose,
Thanks for your response. Please find the schematic in attachment
1. The input nmos is connected in a common source configuration with a current mirror loading. The common source connected nmos is in sub-threshold and current mirror loading is in saturation. The current mirror loading generate the Id for the common source nmos. It seems that my topology fit into "you generate operating current for the amplifier device with a current mirror "Do you think it will cause a problem? Can you please elaborate what kind of the problem?
2. " trade-off occurs when you use the device as a DC current mirror" Are you talking about a different case then 1? I operate the common source amplifier at the edge of the sub-threshold. Does it mean that due to process variation, the common source amplifier could be in deeper sub-threshold or in saturation?

Thank you again!
Allen

 

[frankrose]

1. M16 is a current mirror with M15, yes, and the amplified signal of M15 appears at the gate of M8, which is connected as a common-drain amplifier as I see...It looks like a noise-canceling LNA.
What is you have to be cautious with is the M16 drain current can vary by the mismatch between M16 and M15. Not by the process! Current mismatch of sub-threshold current mirrors are bigger, because the accurate current mirrors need the smallest transconductance as possible (=smallest reachable W/L).
So you should run Monte Carlo simulations to test the performance of your circuit, I don't know exactly how the difference of the transconductance ratios affect the important parameters of the above LNA (gain, in/output impedance, compression, noise figure, etc.).
To supress the effect of mismatch what you can do is to place M15 and M16 in common centroid arrangement definitely.
2. If the device regions change a lot over process, supply voltage and temperature, but the LNA's important parameters are good I think you shouldn't worry...a lot

Extra thoughts:
a, estimate node parasitics (at least capacitance) and add as ideal devices to the critical nodes, simulate with them. they can ruin everything
b, ESD protection + pad model (and those parasitics)
c, series input AC coupling capacitance to eliminate DC path when matching transformer is connected
d, supply noise filtering
e, constant-gm current reference is recommended

LNA design is a challenge, good luck!

 

[AllenD]

Thanks Frankrose!
Yes it is a Noise Canceling LNA. My current layout of the baseline LNA was layout in a most symmetric way possible with common centroid technique.
That's a lot of great suggestions in extra thoughts! At the same time, I am a little overwhelmed.
a) So I can simulate the parasitic caps without using PEX?
c) When I simulate noise figure, the regular impedance of the input port is 50 Ohms. I intentionally change the impedance to 45~55 Ohms to verify the case when the input matching could not supply a exactly 50 Ohms at the gate of the M15. Is that kind of similar with your recommendation?
d) Did you mean PSRR? I fill the circuit with metal mesh blocks. Each of the block is filled with small DC bypass caps. I always assume that the DC bypass is sufficient. Do you agree with my assumption?
e) Could you please elaborate? Did you mean the realization of the current supply at the LNA_IBIAS1 port?

Much obliged!
Allen

 

[frankrose]

a, just estimate some wire lenght, how far is the mixer/antenna pin from the LNA, supply rails distance from signal path, and extract or calculate the parasitic capacitances. Approximate mixer input capacitance too, add worst case value as load. For these you don't have to run PEX.
c, noooo.....and if you designed your LNA for 50 Ohm at the input pin you don't need matching network or impedance transformer. Usually LNAs have higher imput resistance (75...1k Ohm) because the bandwidth is narrow and/or very small noise figure is required next to low power consumption.
d, yes, PSRR, and no, I disagree. Supply noise is the factor of other circuits like the LDO, or digital blocks. And hard to estimate. If you have 1mV inband supply noise, and you don't have just 20dB PSRR the supply noise at the LNA output will be 100uV, probably higher than your amplified input signal...but we don't know your desired sensitivity so, you should know the answer.
e, yes