Description of Physical Compiler tool

Physical compiler

Dear..

thank you for your good suggstion.

first , physical compiler is synopsys commercial tool.
Physical Compiler is a b-level timing convergence tool that
combines proprietary synthesis, placement, and static timing
analysis tools. These tools have a common infrastructure to achieve
the best post-layout quality of results (QOR).
Physical Compiler tightly integrates synthesis and placement; it is
both a synthesis tool and a detailed placement tool. It synthesizes
the logic, places the logic, and performs route estimation that
enables a one-pass timing closure flow. Physical Compiler generates
a design database that describes the optimized netlist and contains
physical placement coordinates specified for the leaf cells. Using this
design database for layout reduces the design cycle time and
improves the QOR.

second, I am very interested in this tool.
because below 0.18um and high gate / technolgy ,
the difference of pre_layout and post_layout is very huge.
below 0.18um , wire delay is bigger than cell delay.
so, this tool is very helpful in chip design.

I hope this content help you.