Dependence of threshold voltage on buried oxide thickness in FD SOI MOSFET

[Jeon.S.B]

Hi all.
I'm simulating 0.2um FD SOI MOSFET using silvaco.
i found if I reduce buried oxide thickness, threshold voltage decrease.
I just mean threshold voltage (not amount of threshold voltage reduction compared with long channel device)
But I don't know the exact dependence between threshold voltage and buried oxide thickness.

Please help me.

 

[dick_freebird]

Your FDSOI MOSFET is really a dual gate device, with
the handle wafer being the second gate and the BOX
being its gate oxide. Generally a thick and inferior one
with a poor surface quality (esp. SIMOX, icky poo).

Your BOX thickness affects that back gate, back will
modulate the evident front gate threshold. The handle
bias and BOX charge trapping are significant, perhaps
more than the BOX thickness alone. I would say that,
therefore, the relationship between VT and tBOX is
-not- exact, and probably not concise.