Delaying a SV program which is instiantiated from top_tb.sv

module te0630_top_tb
// Parameters, Wires and Regs declared

// Top-module instiantiated
te0630_top te0630_top_inst (....) ;

// SysWip AXI BFM connections in TB
   // SysWip AXI master interface inst
   axi4lite_m_if axi_m_if_0(clk);   
   // SysWip AXI slave interface inst
   axi4lite_s_if axi_s_if_0(clk); 
  // Master and slave are connected to the AXI interconnect
  assign .....
  assign ....
  .
  .
  // Call the BFM test program
  axi_bfm_tb axi_bfm_tb_inst() ;  <-- I NEED TO DELAY THE EXECUTON OF THIS INSTIANTIATION  

// Test-bench processes
// clock generation
initial begin
.
.
end

// reset generation
initial begin
.
.
end

// Load a HEX memory
initial begin : nc_program_loader
.
.
end

// some $disply(); statements

endmodule

import AXI4LITE_M::*;
import AXI4LITE_S::*;
import PACKET::*;
typedef bit [7:0]    bit8;

program axi_bfm_tb ();
   initial begin
   // Declare variables
   ...
   // Create class objects
   ...
   // Start BFM environment
   ...
   // Test-cases R-W/W-R, etc
   ...

   end
endprogram

   initial begin
     axi_bfm_tb_reg = 1'b0 ;
     #1000000 axi_bfm_tb_reg = 1'b1 ; // Wait for *time* = 1ms         
   end
   
   axi_bfm_tb axi_bfm_tb_inst() ;

.
.
program axi_bfm_tb ();
   initial begin

   if (te0630_top_tb.axi_bfm_tb_reg == 1'b1) begin
   .
   // Do the AXI tests
   .
   end // end if
   end // end begin
endprogram

  initial begin

   wait (te0630_top_tb.axi_bfm_tb_reg == 1'b1);
   .
   // Do the AXI tests
   .
   end // end begin