Delaying a SV program which is instiantiated from top_tb.sv

[dpaul]

Hello,

The scenario lis like this.
There is a top_tb.sv which is instiantiating a SV program.

module te0630_top_tb
// Parameters, Wires and Regs declared

// Top-module instiantiated
te0630_top te0630_top_inst (....) ;

// SysWip AXI BFM connections in TB
   // SysWip AXI master interface inst
   axi4lite_m_if axi_m_if_0(clk);   
   // SysWip AXI slave interface inst
   axi4lite_s_if axi_s_if_0(clk); 
  // Master and slave are connected to the AXI interconnect
  assign .....
  assign ....
  .
  .
  // Call the BFM test program
  axi_bfm_tb axi_bfm_tb_inst() ;  <-- I NEED TO DELAY THE EXECUTON OF THIS INSTIANTIATION  

// Test-bench processes
// clock generation
initial begin
.
.
end

// reset generation
initial begin
.
.
end

// Load a HEX memory
initial begin : nc_program_loader
.
.
end

// some $disply(); statements

endmodule

Code for the AXI transaction generation between the Master & Slave.

import AXI4LITE_M::*;
import AXI4LITE_S::*;
import PACKET::*;
typedef bit [7:0]    bit8;

program axi_bfm_tb ();
   initial begin
   // Declare variables
   ...
   // Create class objects
   ...
   // Start BFM environment
   ...
   // Test-cases R-W/W-R, etc
   ...

   end
endprogram

I want to delay the execution of the axi_bfm_tb () in the main TB, how to do it?
Reason: In the top_tb.sv the "Load a HEX memory" section does something of its own. Only after this is finished which takes about 1ms, do I want to run the tests for the AXI master and slave.

I tried using #1000000 (1ms delay) inside the axi_bfm_tb (), but it is giving Syntax Errors during simu.

I also tried to SET a register in the top_tb after 1ms and then use that SET value to execute the axi_bfm_tb (), but the simulation dosen't run beyond 0ms!
This is thin top_tb.sv

   initial begin
     axi_bfm_tb_reg = 1'b0 ;
     #1000000 axi_bfm_tb_reg = 1'b1 ; // Wait for *time* = 1ms         
   end
   
   axi_bfm_tb axi_bfm_tb_inst() ;

Then correspondingly in the axi_bfm_tb.sv I was doing this:

.
.
program axi_bfm_tb ();
   initial begin

   if (te0630_top_tb.axi_bfm_tb_reg == 1'b1) begin
   .
   // Do the AXI tests
   .
   end // end if
   end // end begin
endprogram

One way could be to use the code whatever is inside axi_bfm_tb (), in the top_tb, and use the delay after its initial statement. It might be my last option.

But I would prefer to use to delay the initial block in the axi_bfm_tb.sv which is instiantiated in the top_tb.sv?

 

[dave_59]

You need to change your initial block to

  initial begin

   wait (te0630_top_tb.axi_bfm_tb_reg == 1'b1);
   .
   // Do the AXI tests
   .
   end // end begin

Also, according to the SystemVerilog LRM, you are not allowed to access any program block variables from outside the program block. You need to either pass this signal through a port, or my recommendation is to never use a program block and use a module instead. See https://go.mentor.com/programblocks

 

[dpaul]

Thanks Dave!
I am keeping things simple, I am carrying out the entire test in my top_tb.
The program axi_bfm_tb () was some legacy SV test-code and I was reusing.