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I am using Altium designer to draw a layout for my board. My board has two DDR3 and a FPGA.

I have noticed Altium has some tools to estimate the delay and length of the signals (which both should be equal for DDR data lines DDR_DQxx).

I have noticed for some data line signals, if I match the length, the delay would be unmatched.

what should I do? Should I match the delay or length?

I know the final answer is I have to run SI simulation, but I am few steps before simulation.

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